Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

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DisEnchantment

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Mar 3, 2017
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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.
 

Markfw

Moderator Emeritus, Elite Member
May 16, 2002
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call me senile but I prefer to see products on shelves and knowing it's selling in mass amounts before I take intel's word. fool me once, shame on me. fool me twice, shame on you.
Totally. Also, "higher than expected" could be low compared to TSMC's equiv process.
 
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lightisgood

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May 27, 2022
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No specific numbers but an Intel VP, William Grimm, Vice President, Director of Product Engineering for Logic Technology & Development has stated Intel 4 is yielding “higher than expected”




Thank you.
I'd like to add source of non-X.
 

A///

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Feb 24, 2017
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Totally. Also, "higher than expected" could be low compared to TSMC's equiv process.
gonna correct you here, they never mentioned a baseline. it's one of those peculiar statements in the English language that has no floor and no ceiling. They could have expected 500 good wafers a month and only gotten 700 out of a few thousand. it's an extreme example but without numbers their statement's a bit naff and it's why I took issue with it. also this is intel we're talking about.
 

Markfw

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May 16, 2002
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gonna correct you here, they never mentioned a baseline. it's one of those peculiar statements in the English language that has no floor and no ceiling. They could have expected 500 good wafers a month and only gotten 700 out of a few thousand. it's an extreme example but without numbers their statement's a bit naff and it's why I took issue with it. also this is intel we're talking about.
Exactly
 
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Thibsie

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Apr 25, 2017
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gonna correct you here, they never mentioned a baseline. it's one of those peculiar statements in the English language that has no floor and no ceiling. They could have expected 500 good wafers a month and only gotten 700 out of a few thousand. it's an extreme example but without numbers their statement's a bit naff and it's why I took issue with it. also this is intel we're talking about.
They played that card with 10 nm, how many times ? All the times.
 

cortexa99

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Jul 2, 2018
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No specific numbers but an Intel VP, William Grimm, Vice President, Director of Product Engineering for Logic Technology & Development has stated Intel 4 is yielding “higher than expected”


call me senile but I prefer to see products on shelves and knowing it's selling in mass amounts before I take intel's word. fool me once, shame on me. fool me twice, shame on you.


If you are wondering this, some gossip suggested Intel4's manufacturing cost is ~1.8x times of TSMC N6's cost. Source is some comments under leaker 'Golden Pig Upgrade''s Weibo personal page.
 
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Doug S

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Feb 8, 2020
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Totally. Also, "higher than expected" could be low compared to TSMC's equiv process.

I see to remember Intel saying the same "higher than expected" thing about 10nm more than once. If their expectations are low enough, they can exceed them while still having a bad process. If you're going to leak to make yourself look good you would leak the actual yield percentage if it was impressive. Saying "higher than expected" is what you do when the number is embarrassingly low.

After all we've seen graphs where TSMC showed actual yields in the 80% to 90% for processes prior to mass production. With N3 we haven't seen that stuff, instead figures leak like 55%. If they had good N3 yields they would have showed those lovely graphs from the N7 and N5 days.
 

Doug S

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Feb 8, 2020
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Thought this might belong here for people interested in the technology angle. It requires some understanding of current EUV technology to fully grasp what is changing with high NA EUV but is still going to be interesting even if you lack that. I particularly enjoyed a new unit of measurement for power draw - "number of Walmart supercenters". For those outside the US, just imagine the biggest shopping center you've ever seen, then imagine it 'American sized' lol

Interesting comments from the ASML CTO at the end about the affordability of what comes after high NA EUV.

 

Doug S

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Definitely sheds some light on what might have changed for Intel's 20a and 18a processes when they announced an abandonment of High-NA EUV for those nodes.

Supposedly a lot (but far from all) of Intel's troubles with 10nm were related to multipatterning issues. Intel uses self aligned contacts while TSMC never has - apparently they tried to bring it in with the original N3, it caused no end of trouble for them, and it was removed for N3E. I can't help but wonder if TSMC's more "sloppy" alignment tolerance made the relative chaos of multipatterning less of an obstacle for them than it was for Intel.

The problem with not using high NA EUV for 20A/18A is that Intel would be forced into double patterning with EUV - TSMC was quite clear they would had a few multipatterning steps with N2.

Now obviously Intel must have solved those issues one way or another with DUV when they finally got 10nm/Intel 7 to yield, but having to face their old nemesis again this time with EUV can't be a prospect they look forward to. It would not come as a surprise if the removal of high NA EUV from 20A/18A resulted in process changes to relax line widths to minimize multipatterning steps as much as possible, at the cost of power/performance.
 

DrMrLordX

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Apr 27, 2000
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It would not come as a surprise if the removal of high NA EUV from 20A/18A resulted in process changes to relax line widths to minimize multipatterning steps as much as possible, at the cost of power/performance.
Bingo. Actually I suspect some other things as well but we'll see how it all pans out. Intel's launch schedule for 20a and 18a are insanely aggressive, as in I've never seen them release so many nodes in such a short period of time in, I don't know, the last 20 years. Even during their heydey they never pumped out entirely new nodes that quickly.
 

Khato

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Jul 15, 2001
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Even during their heydey they never pumped out entirely new nodes that quickly.
Well, how much of it is an actual change in process development pace versus now playing the same marketing name game as the rest? Was the process used on the historical 'tock' designs exactly the same as the preceding 'tick'? Or was it subject to similar minor improvements that others labeled as a half node increment? I don't really expect that was the case, but I do wonder if that's what we're currently seeing.
 

DrMrLordX

Lifer
Apr 27, 2000
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Well, how much of it is an actual change in process development pace versus now playing the same marketing name game as the rest? Was the process used on the historical 'tock' designs exactly the same as the preceding 'tick'? Or was it subject to similar minor improvements that others labeled as a half node increment? I don't really expect that was the case, but I do wonder if that's what we're currently seeing.
You're asking the same questions I am.

During the height of Intel's power, they locked in their most-recent hegemony on 65nm in 2006, moved to 45nm in late 2007, 32nm in 2010, and 22nm in 2012. Those were all pretty significant jumps in performance and density versus preceding nodes (exception being 22nm that saw some loss in Fmax, but power/density was vastly improved). The average time between full node jumps was ~2 years. Now Intel is supposedly going from Intel 4 to 18a in about the same period of time? Or less? Especially when everyone (including Intel) now takes much longer to release a new, working node in the form of functioning and market-available product? Seems more likely that Intel 3, 20a, and 18a will be incremental upgrades. We already know Intel 3 will be akin to Intel 4+, so does that make 20a 4++ and 18a 4+++?
 
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A///

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You're asking the same questions I am.

During the height of Intel's power, they locked in their most-recent hegemony on 65nm in 2006, moved to 45nm in late 2007, 32nm in 2010, and 22nm in 2012. Those were all pretty significant jumps in performance and density versus preceding nodes (exception being 22nm that saw some loss in Fmax, but power/density was vastly improved). The average time between full node jumps was ~2 years. Now Intel is supposedly going from Intel 4 to 18a in about the same period of time? Or less? Especially when everyone (including Intel) now takes much longer to release a new, working node in the form of functioning and market-available product? Seems more likely that Intel 3, 20a, and 18a will be incremental upgrades. We already know Intel 3 will be akin to Intel 4+, so does that make 20a 4++ and 18a 4+++?
in another 2 years they completed 14nm and we all know what happened after that.
 

Khato

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Jul 15, 2001
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You're asking the same questions I am.

During the height of Intel's power, they locked in their most-recent hegemony on 65nm in 2006, moved to 45nm in late 2007, 32nm in 2010, and 22nm in 2012. Those were all pretty significant jumps in performance and density versus preceding nodes (exception being 22nm that saw some loss in Fmax, but power/density was vastly improved). The average time between full node jumps was ~2 years. Now Intel is supposedly going from Intel 4 to 18a in about the same period of time? Or less? Especially when everyone (including Intel) now takes much longer to release a new, working node in the form of functioning and market-available product? Seems more likely that Intel 3, 20a, and 18a will be incremental upgrades. We already know Intel 3 will be akin to Intel 4+, so does that make 20a 4++ and 18a 4+++?
So first, I'd call Intel 3 a 4+ and 18A a 20A+. That still leaves an unusually short time between Intel 4 and Intel 20A of approximately a year if current roadmaps hold. But this isn't entirely unreasonable considering what 20A is. The current progression from 22nm -> 14nm -> 10nm -> Intel 4 has been primarily scaling focused. Each has provided many tweaks to the FinFET process introduced with 22nm, but the primary challenge and cause for delays have been multi patterning and EUV. My guess is that the Intel 4 -> 20A transition is going to break that trend by not trying to further increase lithography scaling at all and instead rely on RibbonFET + PowerVia to achieve density scaling. And since they're different vectors of process improvement it's likely more feasible to develop all three in parallel.
 

A///

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And since they're different vectors of process improvement it's likely more feasible to develop all three in parallel.
This has been the go to theory some have had on other website forums. Intel litho teams took a leaflet out of AMD's handbook and began working on the nodes in parallel and addressed issues as they popped up. This is still a theory and not something that's been confirmed. Intel making strides in litho is great but the design needs to be great too. One or the other doesn't necessarily preclude failure from ocurring. This is an issue many seem to overlook and only focus on who's making the more dense designs with the fastest performing libraries.