Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

[moinmoin]

Does Intel already have fabs in Israel? I guess Tower could enable local experimental silicon design research for the already existing local Intel design teams. Other than that it sounds like a potential good fit with (also local) Mobileye.

 

[igor_kavinski]

The CPU core isn't derived from Bulldozer, but rather is just using Clustered Multithreading.

That's...a controversial term: The myth of CMT (Cluster-based Multithreading) | Scali's OpenBlog™ (wordpress.com)

So, let’s not pretend that CMT is a valid technology, comparable to SMT. Let’s just treat it as what it is: a hollow marketing term.

 

[NostaSeronx]

That's...a controversial term.

CMT was coined by Charles R. Moore, not by Marketing.

Charles R. Moore (computer engineer) - Wikipedia

en.wikipedia.org

CMT as an idea predates Andy Glew and Charles R Moore at AMD; https://patents.google.com/patent/US6119223A

US6266763B1 - Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values - Google Patents

A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia...

patents.google.com

David B. Witt had lead roles for Am29k, K5, and K7.
James B. Keller is Jim Keller which at the time had a lead role for K8.

Rather than being derived from Charles R. Moore and Mike Butler work, it is derived and changed from the original CMT development.

There is also separate starting points:
AMD's improved am29k/k5 dual-core initial architecture was built in mind with sharing a thread across both cores, as it was penned before AMD's early SMT in K9.
AMD's Bulldozer dual-core initial architecture was built in mind with not-sharing a thread across both cores.
Early CMT = Closely connected cores. Core<->Core at PRF via strong rename unit(Multi-core Mapper).
Bulldozer CMT = Distantly connected cores. Core<->Core at L2 cache.

---
The whole GF FDX stuff is dealing with profit margins and time spent at expenditure(loss) and getting to profit(gain) quick.
+Highest performing digital transistor available at GlobalFoundries at lowest cost of development and production, given at 22FDX w/ GF/SOITEC/Leti Strained SOI in 2H2022 to 2H2023.

 

[eek2121]

https://twitter.com/i/web/status/1493883962728529923

Any bets the customer is Intel?

 

[Markfw]

https://twitter.com/i/web/status/1493883962728529923

Any bets the customer is Intel?

witeken used to post here, and I think at the time was an Intel employee, but not sure now. He was last seen this morning on these forums, but last posting was Jun 27,2020. His LOGO is the Intel trademark.

 

[jpiniero]

witeken used to post here, and I think at the time was an Intel employee, but not sure now.

Definitely no, but shareholder yes.

 

[oak8292]

https://twitter.com/i/web/status/1493883962728529923

Any bets the customer is Intel?

witeken posts as Arne Verheyde on Seeking Alpha and his last post from Feb 10 says that he is still long on Intel but he is neutral on Intel and looking for answers in tomorrows Intel Investor days.

I will speculate that the five 5000 NA EUV research machines will go to Intel, TSMC, Samsung, SKHynix and Micron. Intel has placed the first order for a 5200 NA EUV production machine on January 19, 2022.

Intel and ASML strengthen their collaboration to drive High-NA into manufacturing in 2025 | ASML

Intel makes its first purchase order for ASML’s TWINSCAN EXE:5200 system, marking the next step on the path to EUV 0.55 NA (High-NA) introduction.

www.asml.com

The world is heading to tiles and chiplets. The cost of a 400 mm N2 or 18A die is going to be high with 5200 EUV machines going for 300+ million a piece. Intel is already using some 'tiles' from TSMC and they will also need some RF and silicon photonic tiles on larger geometries to complete SOC, SIP or MCM or whatever multi die nomenclature you want to use. The traditional 'leading edge' has meant the smallest geometry, however, TSMC, Tower, GF and everybody else getting left behind on size has been trying to find ways to 'lead' on larger geometries and there are profits to be made.

 

[DrMrLordX]

Any bets the customer is Intel?

Probably Intel or TSMC.

 

[igor_kavinski]

Moore’s Law – Now and in the Future

Moore’s Law has always been about innovation and we can confidently say innovation continues unabated.

www.intel.com

The long-term progression of Moore’s Law requires overcoming the exponential growth in the power consumption requirements of current CMOS-based computing7. To continue, to scale ultra-low power solutions that use quantum effects in materials (called quantum materials) at ambient room temperatures will be required. In 2021 at IEDM, we reported a huge milestone in beyond-CMOS device research: the first functional demonstration of a magneto-electric spin orbit logic device with its read and write components functional at room temperature. Both the spin orbit output module and a magnetoelectric input module are integrated together into the device, and magnetization state reversals are achieved via applied input voltage. With its ability to realize the higher functionality majority gate (versus NAND and NOR ones) three MESO devices forming ultra-low power majority gates can implement a 1-bit adder, which would otherwise require 28 CMOS transistors

MESO sounds groovy.

 

[Exist50]

Intel Technology Roadmaps and Milestones

At Investor Meeting 2022, Intel shared details on its product and process technology roadmaps and milestones that will drive growth across business segments.

www.intel.com

Looks like there’s some new information here. Most notably numbers for 20A PnP and the 18A timeline.

Ushering in the Angstrom Era with RibbonFET and PowerVia, Intel 20A will deliver up to a 15% performance per watt improvement and will be manufacturing-ready in the first half of 2024. Intel 18A delivers an additional 10% improvement and will be manufacturing-ready in the second half of 2024.

Also, an interesting bit of wording.

Intel remains on track to reclaim transistor performance per watt leadership by 2025.

Might imply that Intel doesn’t think they’ll be ahead in density.

 

[eek2121]

Intel Technology Roadmaps and Milestones

At Investor Meeting 2022, Intel shared details on its product and process technology roadmaps and milestones that will drive growth across business segments.

www.intel.com

Looks like there’s some new information here. Most notably numbers for 20A PnP and the 18A timeline.



Also, an interesting bit of wording.


Might imply that Intel doesn’t think they’ll be ahead in density.

No company gets close to peak (or even average) density for their performance parts. Look at Zen 3, for example.

 

[eek2121]

Everything seems to be in track at Intel:

 

[Exist50]

No company gets close to peak (or even average) density for their performance parts. Look at Zen 3, for example.

Irrelevant. If Intel expected to lead in density in any plausible way, they’d probably mention it.

 

[oak8292]

Everything seems to be in track at Intel:

View attachment 57551
View attachment 57552

It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;

"Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry."

Intel Accelerates Process and Packaging Innovations

Annual cadence of innovations drives leadership from silicon to system.

www.intel.com

It also appears that 18A may be an optimization without a shrink on 20A. The first NA EUV machines won't be available until 2025 per their announcement earlier this year.

Intel appears to have gone to half node advances to mimic what TSMC was doing. It makes sense from a capital perspective since they can't afford to move full nodes on an annual basis. In fact it looks like 20A is a node very similar to TSMC's N10 with a single client product, it will be a 'short lived node' as TSMC would say.

 

[moinmoin]

In fact it looks like 20A is a node very similar to TSMC's N10 with a single client product, it will be a 'short lived node' as TSMC would say.

As long as it's no Cannon Lake again.

 

[dullard]

It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;

I just came here to say that.
For 20A: "expected to ramp in 2024" became "manufacturing-ready in the first half of 2024"
For 18A: "in development for early 2025" became "manufacturing-ready in the second half of 2024"

 

[igor_kavinski]

Things should get very interesting once Intel uses their "process leadership" (that's what they pride themselves on) to make their GPU's scream at 3 GHz and beyond. Less compute units would replace many and then they get to make more GPU dies per wafer.

 

[moinmoin]

once Intel uses their "process leadership" (that's what they pride themselves on)

Are you a time traveler from 2016?

 

[igor_kavinski]

That's what they are aiming for, aren't they? To get back at the top.

 

[maddie]

It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;

"Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry."

Intel Accelerates Process and Packaging Innovations

Annual cadence of innovations drives leadership from silicon to system.

www.intel.com

It also appears that 18A may be an optimization without a shrink on 20A. The first NA EUV machines won't be available until 2025 per their announcement earlier this year.

Intel appears to have gone to half node advances to mimic what TSMC was doing. It makes sense from a capital perspective since they can't afford to move full nodes on an annual basis. In fact it looks like 20A is a node very similar to TSMC's N10 with a single client product, it will be a 'short lived node' as TSMC would say.

"expects to receive the first production tool in the industry."

Does this mean what an earlier member suggested, namely that single machines would go out to the main fabs as evaluation machines giving them the chance to get familiar with using them.

If yes, then this is just another PR job.

Having a smaller market cap than AMD must hurt so badly.

 

[dullard]

"expects to receive the first production tool in the industry."

Does this mean what an earlier member suggested, namely that single machines would go out to the main fabs as evaluation machines giving them the chance to get familiar with using them.

If yes, then this is just another PR job.

Having a smaller market cap than AMD must hurt so badly.

Wow, that just reeks of desperation from you. You turn a comment about receiving a tool into a who has the biggest ___ contest? If you are going to be that petty, so will I. AMD market cap as of the time of your post: $191.52B, INTC: $196.34B. If you are going to be that petty, at least be correct.

 

[oak8292]

GPU's are typically wide and slow to keep them power efficient.

"expects to receive the first production tool in the industry."

Does this mean what an earlier member suggested, namely that single machines would go out to the main fabs as evaluation machines giving them the chance to get familiar with using them.

If yes, then this is just another PR job.

Having a smaller market cap than AMD must hurt so badly.

My understanding is that the ASML 5000 machines being shipped are development machines to 'get familiar'. The ASML 5200 that Intel ordered is supposed to be the first production machine. I don't know where Intel is on process development with the 5000 machine or how many layers will be required for their first NA EUV process.

With the current EUV machines it is roughly one machine per layer per 40 Kwspm. N5 has about 15 layers and to ramp to their target of greater than 100 K wspm they will need around 50 EUV machines. Really rough numbers from a non-expert.

A single machine is probably PR but it is really early for 2025. ASML needs solid orders to get ASML's mirror manufacturer Zeiss to increase production capacity for NA EUV. Lead times are years and not months.

 

[eek2121]

Intel isn’t using High NA for either:

 

[Roland00Address]

Just started, Intel is doing a 3 hour event. Targeted as an Investor Meeting where they are going to be talking things like IDM and other stuff. Here is Dr. Ian Cutress live tweeting it.

https://twitter.com/i/web/status/1494424344793133061

Intel 18A pictured. ( it is SRAM it will be years before CPUs or SOCs are in computers )

 

[IntelUser2000]

So Meteorlake compute tile hasn't been taped out yet? Takes a year so if they want to make it H1 like some people here are expecting they only have few short months to do it assuming it takes exactly 12 months to a product.

This is why I don't like the new "taped-in" terminology. Makes it sound like they are doing more than they are actually doing rather than in the old days where they only said things when tape outs occurred.

Also what is the server chip on the Intel 3 process?

2022 H2 - Sapphire Rapids Intel 7
2023 H2 - Emerald Rapids Intel 7
2024 H2 - Granite Rapids Intel 4? 3?

So Granite Rapids is Intel 3 rather than Intel 4 now? Or they don't need Emerald Rapids anymore? At least good to know that there's something big on Intel 3, otherwise that process would have been dead as a dodo bird.

Update: Ok wow so it looks like Granite Rapids is moving to Intel 3 from Intel 4. Good for them.