That's...a controversial term: The myth of CMT (Cluster-based Multithreading) | Scali's OpenBlog™ (wordpress.com)The CPU core isn't derived from Bulldozer, but rather is just using Clustered Multithreading.
So, let’s not pretend that CMT is a valid technology, comparable to SMT. Let’s just treat it as what it is: a hollow marketing term.
CMT was coined by Charles R. Moore, not by Marketing.That's...a controversial term.
witeken used to post here, and I think at the time was an Intel employee, but not sure now. He was last seen this morning on these forums, but last posting was Jun 27,2020. His LOGO is the Intel trademark.
Definitely no, but shareholder yes.witeken used to post here, and I think at the time was an Intel employee, but not sure now.
witeken posts as Arne Verheyde on Seeking Alpha and his last post from Feb 10 says that he is still long on Intel but he is neutral on Intel and looking for answers in tomorrows Intel Investor days.
MESO sounds groovy.The long-term progression of Moore’s Law requires overcoming the exponential growth in the power consumption requirements of current CMOS-based computing7. To continue, to scale ultra-low power solutions that use quantum effects in materials (called quantum materials) at ambient room temperatures will be required. In 2021 at IEDM, we reported a huge milestone in beyond-CMOS device research: the first functional demonstration of a magneto-electric spin orbit logic device with its read and write components functional at room temperature. Both the spin orbit output module and a magnetoelectric input module are integrated together into the device, and magnetization state reversals are achieved via applied input voltage. With its ability to realize the higher functionality majority gate (versus NAND and NOR ones) three MESO devices forming ultra-low power majority gates can implement a 1-bit adder, which would otherwise require 28 CMOS transistors
Also, an interesting bit of wording.Ushering in the Angstrom Era with RibbonFET and PowerVia, Intel 20A will deliver up to a 15% performance per watt improvement and will be manufacturing-ready in the first half of 2024. Intel 18A delivers an additional 10% improvement and will be manufacturing-ready in the second half of 2024.
Might imply that Intel doesn’t think they’ll be ahead in density.Intel remains on track to reclaim transistor performance per watt leadership by 2025.
No company gets close to peak (or even average) density for their performance parts. Look at Zen 3, for example.Looks like there’s some new information here. Most notably numbers for 20A PnP and the 18A timeline.![]()
Intel Technology Roadmaps and Milestones
At Investor Meeting 2022, Intel shared details on its product and process technology roadmaps and milestones that will drive growth across business segments.www.intel.com
Also, an interesting bit of wording.
Might imply that Intel doesn’t think they’ll be ahead in density.
Irrelevant. If Intel expected to lead in density in any plausible way, they’d probably mention it.No company gets close to peak (or even average) density for their performance parts. Look at Zen 3, for example.
It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;
As long as it's no Cannon Lake again.In fact it looks like 20A is a node very similar to TSMC's N10 with a single client product, it will be a 'short lived node' as TSMC would say.
I just came here to say that.It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;
Are you a time traveler from 2016?once Intel uses their "process leadership" (that's what they pride themselves on)
"expects to receive the first production tool in the industry."It looks like 18A has been moved up. The presentation last year had 18A as a 2025 product;
"Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry."
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Intel Accelerates Process and Packaging Innovations
Annual cadence of innovations drives leadership from silicon to system.www.intel.com
It also appears that 18A may be an optimization without a shrink on 20A. The first NA EUV machines won't be available until 2025 per their announcement earlier this year.
Intel appears to have gone to half node advances to mimic what TSMC was doing. It makes sense from a capital perspective since they can't afford to move full nodes on an annual basis. In fact it looks like 20A is a node very similar to TSMC's N10 with a single client product, it will be a 'short lived node' as TSMC would say.
Wow, that just reeks of desperation from you. You turn a comment about receiving a tool into a who has the biggest ___ contest? If you are going to be that petty, so will I. AMD market cap as of the time of your post: $191.52B, INTC: $196.34B. If you are going to be that petty, at least be correct."expects to receive the first production tool in the industry."
Does this mean what an earlier member suggested, namely that single machines would go out to the main fabs as evaluation machines giving them the chance to get familiar with using them.
If yes, then this is just another PR job.
Having a smaller market cap than AMD must hurt so badly.
"expects to receive the first production tool in the industry."
Does this mean what an earlier member suggested, namely that single machines would go out to the main fabs as evaluation machines giving them the chance to get familiar with using them.
If yes, then this is just another PR job.
Having a smaller market cap than AMD must hurt so badly.