Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[511]

Then you should be glad that he hasn't written any hit pieces on Intel 14A yet.

He is just gambling on Article at this point he will throw random article at Intel to get clicks it may or may not turn out to be true.

 

[Geddagod]

Super low res die shot from techinsights for the exynos 2500 but

X925 on SF3 in Exynos 2500 (apparently a version of SF3 not on the roadmap) : ~2.6mm2
X925 on N3E in Mediatek 9400 (3-2 cells) : ~3mm2
X925 on N3E in Xiaomi xring O1 : ~2.6mm2

The L2 SRAM+tags part of the SF3 X925 appears to be similar in area as the X925 Xring O1 variant as well.

Again, super, super blurry... it's a 876 x 747 pixel image

**not including power gates
Area wise the X925 on SF3E looks comparable. Ofc Fmax is 15-20% faster on the TSMC variant.

X725 on SF3 in Exynos 2500 : ~1.3mm2
X725 on N3E in Xiaomi xring O1 : ~1.15mm2

Area wise the X725 appears marginally larger, if not still outright comparable... but the Fmax of the TSMC variant is ~20% faster.

So after searching for a bit I did manage to find some power data for the Exynos 2500. Unfortunately Geekerwan has not yet covered it yet, but...

10% perf/watt difference at Fmax vs the 9400, ~15% vs the Xring. This sounds much better than it is, IMO, since perf/watt gaps usually are smaller at the rightmost part of the curve than the middle/low end. Could be much higher in that region.
Meanwhile, for the Medium cores:

Similar 10-15% perf/watt difference.

 

[511]

Super low res die shot from techinsights for the exynos 2500 but
View attachment 129649
X925 on SF3 in Exynos 2500 (apparently a version of SF3 not on the roadmap) : ~2.6mm2
X925 on N3E in Mediatek 9400 (3-2 cells) : ~3mm2
X925 on N3E in Xiaomi xring O1 : ~2.6mm2

The L2 SRAM+tags part of the SF3 X925 appears to be similar in area as the X925 Xring O1 variant as well.

Again, super, super blurry... it's a 876 x 747 pixel image

**not including power gates
Area wise the X925 on SF3E looks comparable. Ofc Fmax is 15-20% faster on the TSMC variant.

X725 on SF3 in Exynos 2500 : ~1.3mm2
X725 on N3E in Xiaomi xring O1 : ~1.15mm2

Area wise the X725 appears marginally larger, if not still outright comparable... but the Fmax of the TSMC variant is ~20% faster.

So after searching for a bit I did manage to find some power data for the Exynos 2500. Unfortunately Geekerwan has not yet covered it yet, but...
View attachment 129647
10% perf/watt difference at Fmax vs the 9400, ~15% vs the Xring. This sounds much better than it is, IMO, since perf/watt gaps usually are smaller at the rightmost part of the curve than the middle/low end. Could be much higher in that region.
Meanwhile, for the Medium cores:
View attachment 129648
Similar 10-15% perf/watt difference.

10% weaker than N3E would be right around N4P Ballpark we can use an X4 Core on N4P to compare relative perf and perf/watt for SF3/N3E/N4P.
This would be a N4P performance at N3E density not bad only if they can scale this.

 

[Geddagod]

10% weaker than N3E would be right around N4P Ballpark we can use an X4 Core on N4P to compare relative perf and perf/watt for SF3/N3E/N4P.
This would be a N4P performance at N3E density not bad only if they can scale this.

Mediatek 9400 X4 N3E : ~1.5 mm2 Fmax 3.62 GHz
Mediatek 9300 X4-P N4P : ~1.9 mm2 Fmax 3.25 GHz
Mediatek 9300 X4-M N4P : ~1.6 mm2 Fmax 2.85 GHz

For N4P, you can be ~25% bigger with a ~10% Fmax deficit.
The Mediatek 9300 X4-M only has 512KB of L2 vs the 1MB in the X4-P and X4 in the 9400, however there is an area difference not even considering that (will double check this tmmrw after I go to tn... prob)

Alternatively, we could look at these cores:

Mediatek 9400 A720 N3E : ~0.95 mm2 Fmax 2.4 GHz
Mediatek 9300 A170 N4P : ~0.95 mm2 Fmax 2.0 GHz

For N4P, you can be around the same area, and have a ~15-20% Fmax deficit
The A720 in the 9400 has double the L2 cache I'm too sleepy lol

 

[marees]

What happened to AMD — Sammy partnerships ?

4nm — 2023

https://twitter.com/x/status/1652931486528716800

3nm — 2024

AMD to use Samsung's 3nm tech as it looks to dual-source future chips: report

AMD wants GAAFETs rather earlier than later?

www.tomshardware.com

& 2nm cope — 2025

AMD doesn't rule out Samsung Foundry but declares TSMC the winner for 2nm chips​

Even the spillover from TSMC would be worth billions to Samsung Foundry.

A Senior Vice President at AMD has revealed in an interview that “TSMC is the leader in the 2nm process, so we are focusing on developing and mass producing it with the highest efficiency per watt and semiconductor performance.” This makes it clear that AMD is entirely focused on bringing its 2nm server chips to market with TSMC.

Despite AMD's high praise for TSMC, it has confirmed that the company routinely talks with suppliers “who can offer the best services for our customers.”

 

[adroc_thurston]

What happened to AMD — Sammy partnerships ?

I CAN'T YIELD

 

[adroc_thurston]

(no, seriously, parametric yields on SF3 were atrocious. SF2 tbd, letsa see based off e2600 ramp).

 

[branch_suggestion]

(no, seriously, parametric yields on SF3 were atrocious. SF2 tbd, letsa see based off e2600 ramp).

How about the SF4 deriatives?

 

[adroc_thurston]

How about the SF4 deriatives?

They're fine but nothingburger perf-wise as far as finfets go.

 

[Josh128]

How about the SF4 deriatives?

See Exynos 2200's atrocious clocks.

 

[adroc_thurston]

See Exynos 2200's atrocious clocks.

Old news, 2400 was fine.

 

[511]

* softbank money coming in by the end of the quarter (2 billion)
* customers may like investing only into the foundry business, but splitting the foundries off like that is not very likely any time soon
* LBT getting more confident on 14A
* "corner case" of no external customers for 14A and not building out capacity, pretty confident in 14A getting external customers
* **need external customers for 14A**
* "Milking 18A" for as long as possible haha
* Sounds like Intel is pushing 18A internally much harder than they they will be for 14A
* Putting products on TSMC... forever (will always use external to some extent)
* "Significant" investment for external wafers over the foreseeable future - 70/30 internal vs external now, won't give us numbers for the future lol (though will be more internal in future)
* Using external giving autonomy to product group, and keeping capex in check
* 26' will have a good sense on how 14A is going
* First wave of 18A missed- performance and yield were not ready in time.
* Still opportunity to get customers for 18A - multiple waves of demand- time and effort to get there.
* Very, very early stages for 14A. Good customer engagements (tbh, same thing was said abt 18A lol). Sometime in 26' we will get more detail.
* DMR is 26'- you (Intel) did talk about when it is coming out, Zinsner. Don't say it's being pushed back....
* NVL completely addresses "that situation", has 18A.
* Work to do on the pure design side (for DC specifically?)
* 14A product will be introduced in similar time frame as A14- 28' or 29' timeframe.
* 11 management layers, cut in half by LBT
* Jaguar Shores is still coming out... "soon"
* Notebook share is great, PTL another opportunity.
* Desktop share "not as good", roadmap looks good
* Server, big chunks of market share have completed?, market share more stable than in the past. Not absolutely stable though.
* Margins into the 40s is the goal
* Biggest thing is getting more competitive products for margins

Just some interesting/new/important stuff from the conference. Don't think I missed too much haha.
Credit: @Geddagod

 

[johnsonwax]

11 management layers is still an insane number.

 

[511]

No wonder Intel was a clown show there were no need for this many layers

 

[igor_kavinski]