Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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[511]

I don't hope it doesn't get poof at least we should get a notice period so we can backup bookmarks it was nice knowing you guys
Sayonara

 

[Curious_Inquirer]

To keep the flame going here’s the CoGS of wafers from the Foundries(excluding Intel and Samsung) it’s pretty insane how great TSMC is at controlling costs and make insane amounts of money per wafer. Of course it’s not all leading edge wafers. Plenty of >90nm wafers being produced by everyone. But even then TSMC is in a world of their own in cost efficiency.

 

[511]

To keep the flame going here’s the CoGS of wafers from the Foundries(excluding Intel and Samsung) it’s pretty insane how great TSMC is at controlling costs and make insane amounts of money per wafer. Of course it’s not all leading edge wafers. Plenty of >90nm wafers being produced by everyone. But even then TSMC is in a world of their own in cost efficiency.View attachment 113384View attachment 113385

It is precisely due to their scale

 

[Tigerick]

Samsung might turn to TSMC for new era of Exynos chips

Samsung needs an immediate solution for the success of Exynos chips. The System LSI Division is concerned over the success or failure of its key product. There’s a hope that TSMC may bring a new era of Samsung Exynos chips. Exynos is going through its worst period on Samsung flagships. System...

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Samsung LSI might ask TSMC to make future Exynos due to SF failed to meet the PPA yield in acceptable terms...

 

[Saylick]

It is precisely due to their scale

Yep. The foundry business creates natural monopolies. The scales of economy, especially at the cutting edge, favors one winner taking all.

 

[511]

Samsung might turn to TSMC for new era of Exynos chips

Samsung needs an immediate solution for the success of Exynos chips. The System LSI Division is concerned over the success or failure of its key product. There’s a hope that TSMC may bring a new era of Samsung Exynos chips. Exynos is going through its worst period on Samsung flagships. System...

www.sammyfans.com

Samsung LSI might ask TSMC to make future Exynos due to SF failed to meet the PPA yield in acceptable terms...

Samsung is way worse than Intel foundry in PPA/Yield 🤣

 

[Curious_Inquirer]

Samsung might turn to TSMC for new era of Exynos chips

Samsung needs an immediate solution for the success of Exynos chips. The System LSI Division is concerned over the success or failure of its key product. There’s a hope that TSMC may bring a new era of Samsung Exynos chips. Exynos is going through its worst period on Samsung flagships. System...

www.sammyfans.com

Samsung LSI might ask TSMC to make future Exynos due to SF failed to meet the PPA yield in acceptable terms...

If this turns out to be true then stick a fork in it, Samsung Foundry is done. There’s no more hope in them. TSMC goes from an effective monopoly to an actual monopoly. We’ll be living in TSMC’s world in a few years time if Samsung and Intel don’t get their stuff together and actually deliver on their promises.

 

[511]

If this turns out to be true then stick a fork in it, Samsung Foundry is done. There’s no more hope in them. TSMC goes from an effective monopoly to an actual monopoly. We’ll be living in TSMC’s world in a few years time if Samsung and Intel don’t get their stuff together and actually deliver on their promises.

Intels act is together or not will be known by next year Samsung they haven't given a deadline yet 🤣

 

[511]

To keep the flame going here’s the CoGS of wafers from the Foundries(excluding Intel and Samsung) it’s pretty insane how great TSMC is at controlling costs and make insane amounts of money per wafer. Of course it’s not all leading edge wafers. Plenty of >90nm wafers being produced by everyone. But even then TSMC is in a world of their own in cost efficiency.View attachment 113384View attachment 113385

Data is wrong he didn't calculate correctly it's fixed now

x.com

x.com

 

[Curious_Inquirer]

Oh that makes much more sense now. They’re still making all the money out of the AI craze but not a ridiculous amount of it.

 

[DrMrLordX]

No kidding! This place will go ->POOF<- any day now and people still haven't gotten a consensus on where we're all going.

People can converge on anyf.ca (@Red Squirrel 's forum) until they decide on a final destination should we need a shelter from a fallen forum.

 

[Saylick]

Saw this interesting info get posted on Xitter:

https://twitter.com/x/status/1873044866659434716

 

[igor_kavinski]

That's a pretty significant temp increase. Is Nova Lake gonna need 420mm AIO to perform properly?

 

[maddie]

Saw this interesting info get posted on Xitter:

https://twitter.com/x/status/1873044866659434716

It's worse than that. The two modeled scenarios have equal power values for both FSPD & BSPD designs when comparing temps. One purpose of BSPD is to enable higher power delivery to the processor, meaning the actual temps will be above the max delta shown, with higher performance of course as the benefit.

 

[Hitman928]

Saw this interesting info get posted on Xitter:

https://twitter.com/x/status/1873044866659434716

So are they backing off their claim that they can fully mitigate the increased hot spot effect from BSPDN?

 

[511]

So are they backing off their claim that they can fully mitigate the increased hot spot effect from BSPDN?

Did they even said that cause i have seen everywhere thermal challenges are the biggest hurdle in BSPDN

 

[Saylick]

Did they even said that cause i have seen everywhere thermal challenges are the biggest hurdle in BSPDN

Going to be interesting to see how this affects Intel 18A and its associated products since they've hitched themselves to BSPDN.

 

[Hitman928]

Did they even said that cause i have seen everywhere thermal challenges are the biggest hurdle in BSPDN

Yes, in a previous presentation they said they were able to make the temperature increase negligible if not eliminate it entirely. During the Q&A someone asked how they were able to do this and they just said it was proprietary.

 

[511]

Yes, in a previous presentation they said they were able to make the temperature increase negligible if not eliminate it entirely. During the Q&A someone asked how they were able to do this and they just said it was proprietary.

It was Intel who said this this presentation is IMEC anyways i am curious how they deal with it

I think they are already in the process with Meteor Lake/ARL they are already preparing for this moving the power caps somewhere else and by raising TjMax to 110

 

[Hitman928]

It was Intel who said this this presentation is IMEC anyways i am curious how they deal with it

I think they are already in the process with Meteor Lake/ARL they are already preparing for this moving the power caps somewhere else and by raising TjMax to 110

Gotcha, for some reason I thought it was Intel.

 

[igor_kavinski]

by raising TjMax to 110

Oh no. I hate the smell of hot heatsink metal!

 

[511]

Oh no. I hate the smell of hot heatsink metal!

Bruh...

 

[OneEng2]

Saw this interesting info get posted on Xitter:

https://twitter.com/x/status/1873044866659434716

I guess physics still works, even at Intel.

I had seen this as well. It's a question of clock speed and transistor density combined with metal interconnect resistance combining to make things hot AFAIK.

You can design around it, but at the cost of losing some of that density you gained using BSPD in the first place.

Clearwater Forest will not need to clock very high and will be using efficiency cores. I suspect 18A to be a match made in Heaven for this purpose.

In desktop, this could be a serious problem as it will be in Diamond Ridge. Laptop might work out good as well.

 

[maddie]

Oh no. I hate the smell of hot heatsink metal!

I know, I know, a joke, but on serious note, the heatsink won't be hotter, the hotspots will be. The ΔT between the core and surface will have to increase to compensate for the increased thermal resistance.

 

[Hitman928]

I guess physics still works, even at Intel.

I had seen this as well. It's a question of clock speed and transistor density combined with metal interconnect resistance combining to make things hot AFAIK.

You can design around it, but at the cost of losing some of that density you gained using BSPD in the first place.

Clearwater Forest will not need to clock very high and will be using efficiency cores. I suspect 18A to be a match made in Heaven for this purpose.

In desktop, this could be a serious problem as it will be in Diamond Ridge. Laptop might work out good as well.

It's not the metal interconnect resistance, the metal provides good heat conductance. The problem is that previously, the chips were positioned upside down with the bulk silicon both spreading the heat away from the transistors and providing good thermal conductance up to the next boundary which (combining a few layers together) allows you to interface with the heatsink. With BS-PDN, the chip is no longer upside down and the silicon is thinned down to a very thin layer (relatively), which both limits the ability for the bulk silicon to spread the heat out and introduces significant thermal resistance between the transistors and the next boundary due to all the dielectric layers that now sit between the transistors and the top of the chip.

The thermal resistance is still much less than going out through the socket, so in either case, nearly 100% of the heat still goes towards the heatsink, it's just that you will now have a larger hot spot effect. IMEC and others have published research on methods for partially mitigating the issue, but they aren't fully effective and mostly involve extra TSVs to spread the heat out more from the thinned substrate. There are other proposed methods that would solve it, but it gets pretty exotic and none of which are anywhere near ready for production as far as I know. In terms of density, since the TSVs are now either backside contacts or "Power Via", I don't think you'll need to really effect density to add thermal vias. I agree that most likely the high core count, low power per core products are probably the best fit for backside power. Electrically, it makes a whole lot of sense for high clocking parts to have it too, but unless Intel truly has figured out how to solve the thermal issue, it's hard for me to imagine that they wouldn't be thermally limited to the point of significantly lowered boost clocks without exotic cooling.