Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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DisEnchantment

DisEnchantment

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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

1587737990547.png
N7 performance is more or less understood.
1587739093721.png

This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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1587739615344.png

Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE
 
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mzocyteae

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OneEng2 said:
Using semianalysis.com yield calculator and Panther Lake dimensions of 8mmx14.288 and Intel's reported "D0 < 0.4" (say .36) for 18A you get a yield of 65%.

Using the largest die the equipment can make "Retile Limit" 26mmx33mm you get 7.95% which is <10% .... but meaningless since no one makes a tile that big .... for obvious reasons ;).
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Large chip should use seed and the calc will give 22%. And in practice large chip always has redundancy.
 
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NostaSeronx

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RTX said:
CoolCube already had 100 million vias in 2013/2015 time frame. Any more updates on that?
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The replacement should be shown once the FAMES pilot line pops up.
hisi.jpeg
spring of 2025 (call) -> PDKs (depending on their availability – expect the first PDK to be available in mid 2025) -> FD-SOI 10 nm and 7 nm, embedded non-volatile memory, RF components, 3D integration.

While there is also the SkyWater/GlobalFoundries shared path which should be successor to this:
90nm.jpeg

While looking like this;
omni3dflipfet.jpeg
Omni 3D = Flip FET at Taiwan
 
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name99

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Sep 11, 2010
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OneEng2 said:
That isn't what he said (or at least how I read it).

Pat pointed out (correctly) that Yield is a poor metric, since the same defect density will have different yields on different sizes of die. Larger die will always have lower yields as the probability that a defect will exists will be higher than on a smaller die for the same defect density.

Another point is the type of logic gates being yielded. Some are quite easy to yield high and others quite difficult. The mix of different types of gates in the design makes a big difference to how well the process will actually yield at the end of the day.

What Pat did NOT say, was that the 10% number wouldn't be CORRECT on some size die of some type of logic.

Again, my feeling is that 18A is very likely having issues simply because Intel hasn't come out with some solid metrics related to yield to dispute the rumors. All we have from Intel is "fluffy bunny" and "feel good" statements. Nothing solid.

Granted, TSMC's N2 metrics have been less than complete; however, they have stated they were getting >80% yield on 256Mbit SRAM (which is at least a solid metric for that application). Furthermore, TSMC isn't planning N2 HVM until Q4 2025. Intel, on the other hand, is planning on Panther Lake in "Mid 2025" which sound pretty sketchy to me, considering the lack of information we are seeing on 18A currently.

In all fairness, if TSMC isn't showing solid metrics on N2 by May 2025, then I'll be the first one to start doubting their Q4 targets as well. The current trickle of metrics from TSMC's N2 seem favorable to a Q4 2025 launch while the current trickle of metrics from 18A do not seem favorable to a "Mid 2025" Panther Lake launch.
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Of course D0 isn't the whole story. What are the target power/GHz for PTL?

It could simultaneously be true that 65% of them work (and can in fact be used for driver bringup and fault testing) AND that only 10% meet the target power/GHz numbers...
 
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OneEng2

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Joe NYC said:
Going from 8 full cores using N4 with die size of 70 mm2
to 12 cores on N2 (2 process node advance) with die size of 75 mm2

It seem very doable, especially considering that AVX-512 may go back to half width.
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Maybe, but the desktop and laptop dies will be on N3P I believe.
jur said:
256 Mbit SRAM chip has die size of approx. 7mm^2 (TSMC N2 SRAM density). To get 80% yield one needs defect density less than 3 defects / cm^2, so this really tells us nothing, except that the process probably isn't totally broken.
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I had it estimated at 6mm2 ;).

I agree, but my point is it is more accurate information than Intel. Saying they have D0 < .4 doesn't state what kind of transistors they were making.

I have also heard TSMC saying they are yielding > 60%.... But again, I don't believe they said on what.

Lots of incomplete information so far.
 
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OneEng2

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mzocyteae said:
Large chip should use seed and the calc will give 22%. And in practice large chip always has redundancy.
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That is quite true and a good point; however, it doesn't diminish the fact that despite the information we have to date on 18A and N2, it doesn't complete the picture by a long shot IMO.
name99 said:
Of course D0 isn't the whole story. What are the target power/GHz for PTL?

It could simultaneously be true that 65% of them work (and can in fact be used for driver bringup and fault testing) AND that only 10% meet the target power/GHz numbers...
Click to expand...
Great point. A leading edge node cost an awful lot to be yielding lower clocked parts on. It is only really useful (financially speaking) if it the process can yield chips that have leading edge performance.
 
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QuickyDuck

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Nov 6, 2023
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name99 said:
Of course D0 isn't the whole story. What are the target power/GHz for PTL?

It could simultaneously be true that 65% of them work (and can in fact be used for driver bringup and fault testing) AND that only 10% meet the target power/GHz numbers...
Click to expand...
Exactly! Guys can play with that calculator and it won't tell the whole story.

IIRC, wafer scale chip (biggest chip) have high yields. Because because each chip is so expensive they have to make it work.
 
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OneEng2

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Sep 19, 2022
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SiliconFly said:
Usually, bigger the chip, lower the yield. But this doesn't apply to wafer scale chips cos they're different. For example, Cerebras Wafer Scale Engine (WSE) has lots of built-in redundancies to bypass the defects where ever possible. So, we can't directly use the likes of WSE when discussing yields and defect density.

View attachment 112922
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While true, the basis of the discussion is that D0 (the defect rate per cm2) is also less than complete as it doesn't let you know how "good" the transistors yielded, Maybe they can only clock to 1Ghz? This would still qualify as "good", but would render the process unusable for any high performance tiles.
 
FlameTail

FlameTail

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I have a question: How does using HP libraries affect the power curve of a core compared to the same core on HD library?

In the following figure, you can see how area increases with the use of HP libraries. I wonder... What will this graph look like if the X-axis was Power (Watts), instead of Core Area?
p9ibipzjYpBSVhCE.jpg
 
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igor_kavinski

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Jul 27, 2020
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Win2012R2 said:
As per cheap-MD usual it's going to be on N3 and as per TSMC usual those perf figures are for some test ARM chip at 3 ghz or something :(
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Yeah but if Nova Lake is anything special, AMD's gonna need to have at least a highest possible frequency plan B version of Zen 6. There's no telling if Intel will still pursue tiles with Nova or switch back to monolithic for desktop and reserve tiles only for mobile chips.
 
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Win2012R2

Win2012R2

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AMD should stop mucking around and give CPUs the best process treatment - they are very small dies, so what is price is 50% more - give us the best!

For GPUs that's tough, 10 times area of single Zen chiplet. :(
 
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Meteor Late

Meteor Late

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Dec 15, 2023
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Win2012R2 said:
AMD should stop mucking around and give CPUs the best process treatment - they are very small dies, so what is price is 50% more - give us the best!

For GPUs that's tough, 10 times area of single Zen chiplet. :(
Click to expand...

50% more? Apple is not rising prices in general, or they are small increases.
If AMD loves margins so much, then that's on them, and we as a consumers have all the right in the world to complain, that is called being greedy in my book.
 
Win2012R2

Win2012R2

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Meteor Late said:
50% more?
Click to expand...
50% more per wafer (not final MSPR).

It's not greedy for AMD to have good margins, they need it, but I don't want subpar stuff - 75mm chip that costs double on 2nm is still very cheap, enough consumers will accept $100 extra for really top of the range stuff - very highly clocked with lots of extra 3D cache, stuff like that.

At 75mm AMD should be getting 700+ chiplets per wafer - that's $30 at $20000 wafer price! Yes, sure they will go to servers - but put some into consumer space, sell it for $1k as best CPU available!
 
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