Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[desrever]

Naive question coming.

It seems to me that the main advantages to node shrinks are transistor density and a reduction in power. As the costs of these shrinks and time to make them happen have both become enormous for Intel, when does it become economically smarter to leverage the fact that they have foundry capacity with proven older nodes and to just use them?

For example, let's look at Arrow Lake. If Intel could had the foresight to realize 20A would not be ready they could have designed it for Intel 4 or even Intel 7 if necessary. Yes, the dies would have been larger but the yields would have been there from the start (or nearly so) and they would not be paying the additional fee to outsource to TSMC. In addition, their foundry operations would have been fully utilized. The only real downside I see is efficiency, which they obviously don't care that much about anyway and you can make up for that in MT with more cores at lower clocks, yes I understand that is even more die size. My point is that dies on older nodes is the one thing they can do in house economically.

Note that I'm not talking about backports here. I'm saying if they had the foresight to predict where their process would be when the new architecture was taped out. For the last 10 years they have been unable to make this predictions/forecasts and they simply stalled while the competition caught up. Seems like a smart business decision would have been to just "white flag" efficiency and die size (no one really cares anyway how big their die is) and just go for big numbers, good yields in-house on nodes they have under control.

Desperate times call for desperate measures. At the end of the day Dell, HP, and others just need the volume at good prices, +-10% performance doesn't mean anything to most people shopping in Best Buy or corporate buyers, it's about pricing and reliability.

Theres a limit on how much you can do with how many transistors in a given area as well since it takes time for physical signals to travel and how much distance things can be from something else. There would be significant losses in trying to make something on a larger process thats not just using the same number of transistor.

Also even Intel 4 vs 20A would be massive difference if you consider how much bigger the die needs to be to fit the same number of transistors.

Zen 4 on N5 has 58% more transistor than Zen 3 on N7 while being a small die. To make Zen 4 on N7 would need a die that is >60% bigger. Making something like ARL on Intel 4 would have been possible but probably more expensive and perform worse.

 

[Doug S]

That's the obvious way to do it, but I don't think anyone is doing it that way.
Two alternatives are
- you have two wafers, one built like normal (transistors then signal wiring) and a second that's the power RDL.
Then you mate the two together -- very very accurately...

- the IMEC scheme.
article: https://www.imec-int.com/en/articles/how-power-chips-backside
You build the logic wafer as usual, flip it, remove the silicon (on which the transistors were built) so you have direct access to the transistors, and build your power RDL. (That's simplification, the article gives more details).

I'm pretty sure PowerVia essentially uses the IMEC scheme.
My recollection is that TSMC uses the first scheme I described, but I can't right now find any evidence for that. Maybe I'm misremembering something?

Of course this is more steps! Every new process is more steps, goes with the territory.

I thought mating two wafers was the only way BSPDN could be feasible. Thinning the wafer so much that you can lay down your power rails on the other side sounds almost impossible. It is one thing to thin out already diced DRAMs the size of a fingernail to stack them but handling an entire wafer that's that thin? If that's what Intel is doing, and they can make it work at production yields with the wafers moving around as fast as they do, I guess I will have to admit I'm off about my assessment of what is possible.

One thing I have been wondering about is if you're doing the two wafer method, what stops you from laying down transistors and wiring on that second wafer? I know, sounds crazy, but hear me out. What if those transistors and wiring was VERY regular, so it didn't interfere with the routing of the TSVs? As in SRAM. Lots and lots of juicy SRAM.

If they could make that work then you could reduce the footprint of your design, because all (well almost all, you might leave L1 on die) your cache can be removed. Then you effectively have cache the size of your die as part of the power rail die. You put the CPU L2 over the cores, GPU cache over the GPUs, and so on, and L3/SLC everywhere else.

The cache may be a bit less dense because you have to leave room for the TSVs for the power rails, and because it would make sense to use less dense cache that doesn't require EUV and you need to have TSVs for the signal wiring to connect the cache die to the main die, but you'd have so so much cache and you'd get more chips per wafer thanks to your die being smaller. Would that pay for the extra processing steps and design difficulty? Probably not, but you'd get the performance benefit of all that extra cache.

 

[DrMrLordX]

18A is a do or die for Intel, remember?

Death is always an option.

Also it's funny in your criticism of Pat you mention how he was the one who missed the AI train. Are you some kind of dullard or something, to expect Pat to be able to take advantage of the AI train that hit the industry only 1 year into his position as CEO with intel having comparatively 0 experience in AI vs Nvidia and even AMD.

Intel bought two or three AI companies and had multiple AI products in the pipeline (Loihi and Gaudi come to mind). They had products for learning and inference. They just failed.

 

[SiliconFly]

.

 

[FlameTail]

I thought mating two wafers was the only way BSPDN could be feasible. Thinning the wafer so much that you can lay down your power rails on the other side sounds almost impossible.

The thinned wafer is placed on another support wafer.

This well researched video by High Yield explains it.

 

[igor_kavinski]

You seem to hate Intel so much, have you invested in AMD shares?

I don't hate them in the sense I hate Nvidia (<<<evil). I have a 12700K and I just got a 245K to play with and I will probably get the ARC B780 or whatever the high end Battlemage card they release in 2025. My only problem with Intel was their continued mistakes starting from the hybridization of Alder Lake and then following up those mistakes with more mistakes for which Pat has to take full responsibility because he's supposed to be the engineer who knows better than us. Arrow Lake should never have been released in its current state. His decisions seemed panicky and he was rightfully ousted. He had no idea what to do. The "future is going to be GREAT" shtick doesn't work with me and I'm glad that it didn't work with the board. Hoping for the best for Intel's future.

 

[igor_kavinski]

Intel bought two or three AI companies and had multiple AI products in the pipeline (Loihi and Gaudi come to mind). They had products for learning and inference. They just failed.

Maybe their AI gurus just gained experience and left for greener pastures, leaving behind clueless idiots

 

[OneEng2]

Intel never earn $1 from node,but without lead node,intel never earn $.
Every otherone become brilliant after intel lose the lead node.The lead node is everything for intel, and the nightmare to any otherone.

Arrow Lake is being produced on a process node that is superior to the one that AMD's Zen 5 is produced on and yet it is largely behind in most every benchmark.

Intel's (and many here) "argument" is that Intel nodes are fundamentally better nodes than any other foundry has (which has traditionally been true as well). The argument then goes on to say that Intel processors built on Intel process will be superior to the competition and demand higher prices and sell more. Correct?

It all sounds great until you start filling out the butchers bill and cost out what you are ACTUALLY paying for those chips at Intel. 18A is estimated to cost Intel around 10bn USD. That is about the price of a US Navy Ford class aircraft carrier. The cost of each wafer is also expensive with GAA and BSPDN. The overhead of having an entire infrastructure for the fab is expensive, etc, etc. And the bottom line is that Intel is losing tens of billions of dollars a quarter.

Intel can't just raise the price of their processors times 2 to become profitable. No one would buy them. So how does this work?

Naive question coming.

It seems to me that the main advantages to node shrinks are transistor density and a reduction in power. As the costs of these shrinks and time to make them happen have both become enormous for Intel, when does it become economically smarter to leverage the fact that they have foundry capacity with proven older nodes and to just use them?

For example, let's look at Arrow Lake. If Intel could had the foresight to realize 20A would not be ready they could have designed it for Intel 4 or even Intel 7 if necessary. Yes, the dies would have been larger but the yields would have been there from the start (or nearly so) and they would not be paying the additional fee to outsource to TSMC. In addition, their foundry operations would have been fully utilized. The only real downside I see is efficiency, which they obviously don't care that much about anyway and you can make up for that in MT with more cores at lower clocks, yes I understand that is even more die size. My point is that dies on older nodes is the one thing they can do in house economically.

Note that I'm not talking about backports here. I'm saying if they had the foresight to predict where their process would be when the new architecture was taped out. For the last 10 years they have been unable to make this predictions/forecasts and they simply stalled while the competition caught up. Seems like a smart business decision would have been to just "white flag" efficiency and die size (no one really cares anyway how big their die is) and just go for big numbers, good yields in-house on nodes they have under control.

Desperate times call for desperate measures. At the end of the day Dell, HP, and others just need the volume at good prices, +-10% performance doesn't mean anything to most people shopping in Best Buy or corporate buyers, it's about pricing and reliability.

I think their issues are deeper than even that. Intel can't amortize their equipment over nearly as many chips as TSMC does. This is further exasperated by Intel's philosophy of selling older equipment and saving fab space for only newer nodes while paying external fabs to make their chips for the older nodes.

Additionally, Intel has been an integrated design house for so long, their entire tool chain and process is unfriendly to the on-boarding of an external customer. Their processes are also highly tailored to their own products vs the industry in general further dissuading external companies from wanting to use their fab house as the pain of porting existing designs becomes expensive and risky vs TSMC.

AMD ran into a similar issue because "Real Men Have Fabs" . It was crazy expensive for them to part with this idea, and it took a few design cycles to recover IIRC. Intel will need to undergo a similar restructuring and philosophy change as well IMO.

 

[Hulk]

Arrow Lake is being produced on a process node that is superior to the one that AMD's Zen 5 is produced on and yet it is largely behind in most every benchmark.

Intel's (and many here) "argument" is that Intel nodes are fundamentally better nodes than any other foundry has (which has traditionally been true as well). The argument then goes on to say that Intel processors built on Intel process will be superior to the competition and demand higher prices and sell more. Correct?

It all sounds great until you start filling out the butchers bill and cost out what you are ACTUALLY paying for those chips at Intel. 18A is estimated to cost Intel around 10bn USD. That is about the price of a US Navy Ford class aircraft carrier. The cost of each wafer is also expensive with GAA and BSPDN. The overhead of having an entire infrastructure for the fab is expensive, etc, etc. And the bottom line is that Intel is losing tens of billions of dollars a quarter.

Intel can't just raise the price of their processors times 2 to become profitable. No one would buy them. So how does this work?

I think their issues are deeper than even that. Intel can't amortize their equipment over nearly as many chips as TSMC does. This is further exasperated by Intel's philosophy of selling older equipment and saving fab space for only newer nodes while paying external fabs to make their chips for the older nodes.

Additionally, Intel has been an integrated design house for so long, their entire tool chain and process is unfriendly to the on-boarding of an external customer. Their processes are also highly tailored to their own products vs the industry in general further dissuading external companies from wanting to use their fab house as the pain of porting existing designs becomes expensive and risky vs TSMC.

AMD ran into a similar issue because "Real Men Have Fabs" . It was crazy expensive for them to part with this idea, and it took a few design cycles to recover IIRC. Intel will need to undergo a similar restructuring and philosophy change as well IMO.

Zen 5 is more performant than ARL due to architecture, not process. ARL beats Zen 5 handily in some benches due to architectural differences.

ARL on Intel 4 would have been larger but how much more expensive to produce when they don't have to outsource? Plus the benefits of keeping their foundry running.

Plus perhaps the benefit of getting it out a year earlier.

Perhaps Intel needs to go back to the old tick-tock strategy. What I mean by that is put out the new architecture on a proven, working, good yielding node and rely on good architecture for performance. Then update with a process shrink when the process is ready. They go for architecture and process simutaneously and it's been a disaster.

 

[maddie]

AMD ran into a similar issue because "Real Men Have Fabs" . It was crazy expensive for them to part with this idea, and it took a few design cycles to recover IIRC. Intel will need to undergo a similar restructuring and philosophy change as well IMO.

This had me cracking up. I'm sure (?) you didn't mean it, but the great Western uncertainty these days appear to relate to this. I'm trying to be very diplomatic here.

 

[RTX]

It was only fabless firms claiming 28nm and below continued to increase in cost per transistor?

 

[OneEng2]

This had me cracking up. I'm sure (?) you didn't mean it, but the great Western uncertainty these days appear to relate to this. I'm trying to be very diplomatic here.

Glad you got a chuckle . It was a quote from the AMD original CEO Jerry Sanders in the mid 90's.

Ironically, AMD didn't really make a profit until they got rid of the fabs. I guess it wasn't that profitable being a "Real Man" .

 

[igor_kavinski]

I guess it wasn't that profitable being a "Real Man" .

I think most men with wives would agree

 

[OneEng2]

I think most men with wives would agree

LMAO. As a man with a wife, I most certainly agree. Thanks for the laugh

 

[ajsdkflsdjfio]

Intel bought two or three AI companies and had multiple AI products in the pipeline (Loihi and Gaudi come to mind). They had products for learning and inference. They just failed.

Unless they bought Nvidia itself, don't really see how that puts them in a good position to compete. Like if Intel bought Glofo or even Samsung it certainly wouldn't automatically make them a contender for top foundry.

 

[desrever]

Unless they bought Nvidia itself, don't really see how that puts them in a good position to compete. Like if Intel bought Glofo or even Samsung it certainly wouldn't automatically make them a contender for top foundry.

Intel is losing to not just Nvidia but everyone else trying to pick up the scraps too. If they had more vision, they could have been 2nd or 3rd but now it looks like they are lucky to be in the top 10.

 

[jpiniero]

Intel is losing to not just Nvidia but everyone else trying to pick up the scraps too. If they had more vision, they could have been 2nd or 3rd but now it looks like they are lucky to be in the top 10.

I'm not sure there's room for much other than NV and AMD getting the scraps.

 

[ajsdkflsdjfio]

Intel is losing to not just Nvidia but everyone else trying to pick up the scraps too. If they had more vision, they could have been 2nd or 3rd but now it looks like they are lucky to be in the top 10.

Who are the top ten? I'm not exactly following the AI market but Nvidia, AMD, Tenstorrent, maybe cerebras? Intel is 3rd among that list. The only other contenders I can think of are large companies like AWS making their own chips but that is a completely separate thing.

 

[desrever]

Who are the top ten? I'm not exactly following the AI market but Nvidia, AMD, Tenstorrent, maybe cerebras? Intel is 3rd among that list. The only other contenders I can think of are large companies like AWS making their own chips but that is a completely separate thing.

The obvious ones you listed and the cloud companies that have their own AI chips. Intel is probably behind all of them. And with their current product and their roadmap, its not likely they are competitive with any of them soon.

Gaudi is a dead end at this point and sales are under 500 million this year, who knows if they can improve it next year. Falcon shores might be behind where AMD is now.

 

[ajsdkflsdjfio]

The obvious ones you listed and the cloud companies that have their own AI chips. Intel is probably behind all of them. And with their current product and their roadmap, its not likely they are competitive with any of them soon.

Gaudi is a dead end at this point and sales are under 500 million this year, who knows if they can improve it next year. Falcon shores might be behind where AMD is now.

Like I said, the cloud companies making their own chips are a completely separate market. Even If Intel were no 2 or no 1 the cloud companies would still be making their chips, they aren't eating away at the overall market share since they weren't part of the market in the first place, they aren't competitors. If anything them producing chips is only hurting Nvidia not Intel or AMD. I agree Gaudi has fell extremely short of what Intel predicted. But Intel is basically where you'd expect them to be in the publicly available AI chip market, behind Nvidia and AMD who have been doing this for a much longer time than Intel and were slated to benefit from the AI chip boom day one. Do you expect Qualcomm to be able to enter the laptop/desktop market and be anything but a sideline player for years to come. On one hand Intel is failing to even compete in it's core businesses, now you expect Intel to be able to compete in markets they have comparatively no experience in?

 

[igor_kavinski]

On one hand Intel is failing to even compete in it's core businesses, now you expect Intel to be able to compete in markets they have comparatively no experience in?

Wish someone could've told that to Intel's board

 

[The Hardcard]

Glad you got a chuckle . It was a quote from the AMD original CEO Jerry Sanders in the mid 90's.

Ironically, AMD didn't really make a profit until they got rid of the fabs. I guess it wasn't that profitable being a "Real Man" .

IBM paid Globalfoundries some billions of dollars to take their fabs.

 

[name99]

I thought mating two wafers was the only way BSPDN could be feasible. Thinning the wafer so much that you can lay down your power rails on the other side sounds almost impossible. It is one thing to thin out already diced DRAMs the size of a fingernail to stack them but handling an entire wafer that's that thin? If that's what Intel is doing, and they can make it work at production yields with the wafers moving around as fast as they do, I guess I will have to admit I'm off about my assessment of what is possible.

One thing I have been wondering about is if you're doing the two wafer method, what stops you from laying down transistors and wiring on that second wafer? I know, sounds crazy, but hear me out. What if those transistors and wiring was VERY regular, so it didn't interfere with the routing of the TSVs? As in SRAM. Lots and lots of juicy SRAM.

If they could make that work then you could reduce the footprint of your design, because all (well almost all, you might leave L1 on die) your cache can be removed. Then you effectively have cache the size of your die as part of the power rail die. You put the CPU L2 over the cores, GPU cache over the GPUs, and so on, and L3/SLC everywhere else.

The cache may be a bit less dense because you have to leave room for the TSVs for the power rails, and because it would make sense to use less dense cache that doesn't require EUV and you need to have TSVs for the signal wiring to connect the cache die to the main die, but you'd have so so much cache and you'd get more chips per wafer thanks to your die being smaller. Would that pay for the extra processing steps and design difficulty? Probably not, but you'd get the performance benefit of all that extra cache.

There are actually a few different ways to do it. I gave the Imec link earlier; a simpler discussion can be found here:

Clash of the Foundries: Gate All Around + Backside Power at 2nm

Fab Cost, SRAM Scaling, WFE Implications, Backside Power Details, TSMC, Samsung, Intel, Rapidus TSMC won FinFET. All noteworthy leading edge logic designs, even Intel’s, are manufactured on TS…

semianalysis.com

I think everyone agrees that a second layer of cache is coming. (Well, everyone who hasn't designed themselves into a GHz kW corner, and so who can handle the thermals of such an additional layer...)
So at that point it's mostly a question of costs and timing as to exactly how it's done! And that's basically impossible for us as outsiders to predict :-(

The other unexpected use case of the backside (clocks, and some signals are obvious use cases) is building lots of localized capacitors, which in turn allow you to shave your voltage a little and save a little more power. Not very sexy, but if using this gets you 5% less power "for free" (except the additional design effort) why not?

 

[name99]

Unless they bought Nvidia itself, don't really see how that puts them in a good position to compete. Like if Intel bought Glofo or even Samsung it certainly wouldn't automatically make them a contender for top foundry.

Apple and Google trained on TPU.
Apple will train their next generation of models on AWS Trainium.
Cerebras is selling so well they don't need to spend anything on advertising.

It's absolutely possible to compete with nVidia, either for training or for inference. If Intel is incapable of doing so (while Google and AWS both are not, and for Apple on the inference side) that's a problem with Intel.

nVidia has plenty of advantage for academics and I understand why so many papers (ie ideas) are prototyped on nV. But once you're ready to scale to weeks of training, another product can absolutely compete, whether their special sauce is easy connectivity to warehouse size, or massive on-chip SRAM, or whatever.

 

[name99]

Who are the top ten? I'm not exactly following the AI market but Nvidia, AMD, Tenstorrent, maybe cerebras? Intel is 3rd among that list. The only other contenders I can think of are large companies like AWS making their own chips but that is a completely separate thing.

It's not a completely separate thing.
It's proof that Intel didn't even bother to go to the most obvious large purchasers and create something tailored to their needs...

It feels like Intel ran their playbook from the 1990s with AI. They assumed that the target market should be "workstations" (something basically for an individual, paid for by a department). Which meant they were
(a) competing directly with nVidia in terms of Hopper or Blackwell cards
(b) ignoring by far the largest purchasers.

Basically mobile all over again, in the opposite direction - saying "we don't understand this market and have never designed for it, so we'll pretend that the market we do understand is all that matters".