Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

[DisEnchantment]

TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.


N7 performance is more or less understood.


This year and next year TSMC is mainly increasing capacity to meet demands.

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For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.

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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE

 

[511]

It's over for x86 and ARM Samsung Killed it.

https://twitter.com/x/status/1984777565995684204

 

[poke01]

It's over for x86 and ARM Samsung Killed it.

https://twitter.com/x/status/1984777565995684204

you know its fake when they mention 384-bit memory bus

 

[511]

you know its fake when they mention 384-bit memory bus

 

[marees]

Ap

you know its fake when they mention 384-bit memory bus

Apparently it is a test board. Real apu (if it gets released) will not have that

https://twitter.com/x/status/1984890770508157329

 

[Josh128]

Arent we getting to the point where some more Panther Lake CPU leaks should be springing? I know "Q4 2025" is a paper launch, but the silence is starting to deafen a bit.

 

[511]

Arent we getting to the point where some more Panther Lake CPU leaks should be springing? I know "Q4 2025" is a paper launch, but the silence is starting to deafen a bit.

I am pretty sure they have tighten the leash around leaks and stuff.
Also we get GB AI Leaks Like we get Geekbench AI on CPU with ONNX like what the actual .... It would have been better to not run that.

 

[dangerman1337]

Arent we getting to the point where some more Panther Lake CPU leaks should be springing? I know "Q4 2025" is a paper launch, but the silence is starting to deafen a bit.

I mean actual products with it probably not until March of next year or even longer since there's a usual lag time of Laptop CPUs being announced and taking months for them to come out.

 

[poke01]

I am pretty sure they have tighten the leash around leaks and stuff.
Also we get GB AI Leaks Like we get Geekbench AI on CPU with ONNX like what the actual .... It would have been better to not run that.

It’s like OEMs are scared to run Geekbench CPU, you know the most interesting one and the one that has the ability to make some news.

 

[511]

It will be like 5% faster in GB ST vs ARL-H ... Good enough for a refresh

 

[fastandfurious6]

ARL-H not HX? so slower than HX?

 

[MoistOintment]

Arent we getting to the point where some more Panther Lake CPU leaks should be springing? I know "Q4 2025" is a paper launch, but the silence is starting to deafen a bit.

The leakers' Intel contacts got caught up in the mass layoffs and they're scrambling to find new ones /s

 

[marees]

Musk, OpenAI, & US govt to invest further in Intel ???

(Musk complains that chips have become a bottleneck for Tesla)

https://twitter.com/x/status/1986585317995171980

 

[johnsonwax]

Musk, OpenAI, & US govt to invest further in Intel ???

(Musk complains that chips have become a bottleneck for Tesla)

Understand that all of that is Musk setting his $1T paycheck targets and then theory crafting all of the steps from where they are to where he needs to be to collect that paycheck regardless of whether they are in any way realistic or even possible.

If he thinks that TSMC is too much of a bottleneck, wait until he meets ASML.

 

[Doug S]

Understand that all of that is Musk setting his $1T paycheck targets and then theory crafting all of the steps from where they are to where he needs to be to collect that paycheck regardless of whether they are in any way realistic or even possible.

If he thinks that TSMC is too much of a bottleneck, wait until he meets ASML.

Not just them. Fabs have all kinds of complex devices with few or even one vendor who have set their production schedules based on order forecasts from established players. If some trillionaire on a ketamine bender wants to build something that rivals TSMC's ENTIRE wafer output but all on the leading edge even if he could magically get enough EUV machines from ASML and steal TSMC's process recipes he's still gonna have multiple Everest sized mountains to scale on the way to Shangri La.

Heck, I have to wonder if even something as relatively simple as the production of silicon ingots they slice the wafers from could be a bottleneck. They've already had to scale it a lot to account for new packaging technologies, and now all the pressure on DRAM/NAND vendors that's causing the price increases. They might already be running at capacity and any link in that chain of production could break his dreams even before the ketamine wears off.

 

[johnsonwax]

Not just them. Fabs have all kinds of complex devices with few or even one vendor who have set their production schedules based on order forecasts from established players.

If some trillionaire on a ketamine bender wants to build something that rivals TSMC's ENTIRE wafer output but all on the leading edge even if he could magically get enough EUV machines from ASML and steal TSMC's process recipes he's still gonna have multiple Everest sized mountains to scale on the way to Shangri La.

Heck, I have to wonder if even something as relatively simple as the production of silicon ingots they slice the wafers from could be a bottleneck. They've already had to scale it a lot to account for new packaging technologies, and now all the pressure on DRAM/NAND vendors that's causing the price increases. They might already be running at capacity and any link in that chain of production could break his dreams even before the ketamine wears off.

My son is an electrical engineer for one such company. They make control hardware for the industry. And while they can scale, I'm not sure they'd take Tesla as a customer given their history of unreasonable demands. They aren't so large that a Tesla couldn't wipe them out. I know they have very good trust relationships with their primary customers because in that sense, it's a tight-knit industry. My understanding is that whole system still largely works because everyone understands their role and they aren't combative in, say, the Trump/Musk sense of negotiating which is very confrontational and combative. The different players all know they are trying to move the industry forward and they do so in a much more respectful/cooperative sense because there are SO many different potential points of failure and burning a bridge with one of the very few players one layer up/down from you isn't beneficial in the long term.

 

[Joe NYC]

Understand that all of that is Musk setting his $1T paycheck targets and then theory crafting all of the steps from where they are to where he needs to be to collect that paycheck regardless of whether they are in any way realistic or even possible.

If he thinks that TSMC is too much of a bottleneck, wait until he meets ASML.

It's more feasible for Musk to expand his partnership with Samsung, which already has most of the infrastructure in place, even process technology in place, all it is fine tuning to process technology.

And, as much as Musk needs a supplier, Samsung needs a big customer.

 

[johnsonwax]

It's more feasible for Musk to expand his partnership with Samsung, which already has most of the infrastructure in place, even process technology in place, all it is fine tuning to process technology.

And, as much as Musk needs a supplier, Samsung needs a big customer.

Musk doesn't just need a supplier, he needs technology that hasn't yet been invented and a demand market that doesn't exist. Those are much harder to get. He acting not just that Teslas robot army will exist but that it'll be large enough and useful enough to need a general. Usually you hit your supplier bottleneck after you've got a functional prototype. He seems to have one before that.

 

[sdifox]

Well right on my cue after my posts last night about no one in the west doing FEL, here's a startup uncloaking this morning that says they're doing FEL. Gonna need way more than its initial $100 million to make it happen though.

https://www.bloomberg.com/news/arti...hip-startup-seeking-to-crack-asml-s-dominance

https://twitter.com/x/status/1983156803895734435

Zee Germans disagree!

K. Ferdinand Braun - Wikipedia

en.wikipedia.org

 

[Fjodor2001]

Does anyone who what the current estimate is for when we will hit the wall w.r.t. process node advancements?

We have 10-14A in the roadmaps (but unknown after that?), and a silicon atom is 1.9-2.3A depending on how/what is measured, IIRC.

 

[jpiniero]

Does anyone who what the current estimate is for when we will hit the wall w.r.t. process node advancements?

We have 10-14A in the roadmaps (but unknown after that?), and a silicon atom is 1.9-2.3A depending on how/what is measured, IIRC.

Most likely they will hit a cost wall first than technical feasibility.

 

[Fjodor2001]

Most likely they will hit a cost wall first than technical feasibility.

Ok, why do you think that, and at approximately what X Ångström will that cost wall be hit?

 

[techjunkie123]

Ok, why do you think that, and at approximately what X Ångström will that cost wall be hit?

Afaik the features are not close to 10-14 A yet....The cell size for 2nm is about 150 x 50 nm I think. Still pretty far from atomic dimensions.

 

[Fjodor2001]

Afaik the features are not close to 10-14 A yet....The cell size for 2nm is about 150 x 50 nm I think. Still pretty far from atomic dimensions.

But is it expected that the limit will be 1 atomic dimension for silicon (i.e. 1.9-2.3A), and if so why?

Sounds pretty impressive/unrealistic, even if the cells will be wider than that.

 

[LightningZ71]

If they are still using electricity and silicon, the limit will have to be far larger than a single outer electron shell radius. There has to be sufficient resistance to electron traversal between atoms associated with different transistors to allow sufficient potential for proper operation. In addition,you are going to hit a thermal density wall VERY soon that is going to be quite difficult to scale past. Each XTOR generates heat, and it must go somewhere. If they are packed in too tight, there isn't enough "somewhere" that isn't already saturated with heat to keep the XTORs in their operational temperature range.

 

[johnsonwax]

Ok, why do you think that, and at approximately what X Ångström will that cost wall be hit?

So the capital costs scale non-linearly to the size gain, which means you need a corresponding volume of demand to cover that capital cost. That demand seems increasingly artificial (AI, etc.) and unsustainable.

We've done this before - the days of single core CPUs started to hit GHz scaling problems and we moved to multi core to deliver more performance at a lower cost per performance unit. We've been doing more asymmetrical compute - moving from CPU to CPU+GPU to CPU+GPU+TPU. Local/network factors into this - why spend a lot of money on desktop compute that's only being used 40 hours a week and isn't paying for itself 128 hours a week when you can shift that compute to datacenter and get a lot closer to 168 hours per week of utilization due to timezones and cost sharing across uses and so on.

If you look at the larger law of accelerating returns of which Moores law is merely a local implementation of, it takes all kinds of weird forms over time - the printing press allowing you to share 'yo, there's this calculus thing', slide rules and cheap printed logarithm tables to speed up calculations, and so on. The compute field over indexes on Moores law as the solution to the law of accelerating returns in the silicon space, but it's just one solution, and also the most easily measured solution but it's not the solution. I mean, Cisco probably unlocked more compute opportunity for the average person than Intel did because networking scales so much better than foundry process does.