Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel) - [2020 - 2025]

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DisEnchantment

Golden Member
Mar 3, 2017
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TSMC's N7 EUV is now in its second year of production and N5 is contributing to revenue for TSMC this quarter. N3 is scheduled for 2022 and I believe they have a good chance to reach that target.

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N7 performance is more or less understood.
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This year and next year TSMC is mainly increasing capacity to meet demands.

For Samsung the nodes are basically the same from 7LPP to 4 LPE, they just add incremental scaling boosters while the bulk of the tech is the same.

Samsung is already shipping 7LPP and will ship 6LPP in H2. Hopefully they fix any issues if at all.
They have two more intermediate nodes in between before going to 3GAE, most likely 5LPE will ship next year but for 4LPE it will probably be back to back with 3GAA since 3GAA is a parallel development with 7LPP enhancements.


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Samsung's 3GAA will go for HVM in 2022 most likely, similar timeframe to TSMC's N3.
There are major differences in how the transistor will be fabricated due to the GAA but density for sure Samsung will be behind N3.
But there might be advantages for Samsung with regards to power and performance, so it may be better suited for some applications.
But for now we don't know how much of this is true and we can only rely on the marketing material.

This year there should be a lot more available wafers due to lack of demand from Smartphone vendors and increased capacity from TSMC and Samsung.
Lots of SoCs which dont need to be top end will be fabbed with N7 or 7LPP/6LPP instead of N5, so there will be lots of wafers around.

Most of the current 7nm designs are far from the advertized density from TSMC and Samsung. There is still potential for density increase compared to currently shipping products.
N5 is going to be the leading foundry node for the next couple of years.

For a lot of fabless companies out there, the processes and capacity available are quite good.

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FEEL FREE TO CREATE A NEW THREAD FOR 2025+ OUTLOOK, I WILL LINK IT HERE
 
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coercitiv

Diamond Member
Jan 24, 2014
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The copium side of me is saying Softbank knows something we don't about external customer using Intel lol.
They probably got wind of the idea that US Gov will invest, and they think it's likely to happen:
 
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511

Diamond Member
Jul 12, 2024
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Really? Sold NV at 4.7X returns compared to 4T market capital ?


Watch this video before you talk non-sense as usual.
Just got the summary from somewhere also since when do I talk none sense usual I rarely do that.
 

Josh128

Golden Member
Oct 14, 2022
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What does the "more than half of them can move 6+" mean? Six+ cores working out of 4+8?
Nobody knows, how tf is anyone supposed to know with non-sensical statements such as that? If more than half is 6+ and best is 5+, that makes no sense in the context you are reading it. One thing for certain, 40% to 50% "salvageable" dies (if that what this means) for a process that was supposed to be shipping products next quarter is horrible. Thats all we need to know.

Look at this roadmap. 18A was supposed to be ready/shipping in 2024. Yielding 50% on mobile compute dies at the end of 2025 is a bonafide disaster going by this graphic. For context, Pat released this in February of 2024.

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511

Diamond Member
Jul 12, 2024
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Nobody knows, how tf is anyone supposed to know with non-sensical statements such as that? If more than half is 6+ and best is 5+, that makes no sense in the context you are reading it. One thing for certain, 40% to 50% "salvageable" dies (if that what this means) for a process that was supposed to be shipping products next quarter is horrible. Thats all we need to know.
That 50% is parametric yield not Physical yield their physical yield very will be higher also can't 6+ refer to U7/U9 perhaps and the last line says the clock is 5+ GHz which has been known.
If they have reach HVM D0(<~0.15) and 40-50% parametric yield as of now they can wait for 1-2 months for it to reach higher and than enter HVM it's their call
 
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Win2012R2

Golden Member
Dec 5, 2024
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Not even N5 and N3 rules are design compatible you should research a bit before asking such stuff.
Well exactly - so that's extra cost of porting which isn't as trivial as paying $$$ for masks = non starter, might as well port to Samsung and get it at cost.
 
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511

Diamond Member
Jul 12, 2024
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he company is running in Chaos will someone rein in chaos or will the chaos consume them.
Stay Tuned to find out
 

511

Diamond Member
Jul 12, 2024
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Well exactly - so that's extra cost of porting which isn't as trivial as paying $$$ for masks = non starter, might as well port to Samsung and get it at cost.
Might as well not do stuff at Samsung Samsung didn't had a good yielding process since 8nm
 

DavidC1

Platinum Member
Dec 29, 2023
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Look at this roadmap. 18A was supposed to be ready/shipping in 2024.
That's foundry readiness. Intel 3 products came out in late 2024. 18A was supposed to be late 2025 with Clearwater but got delayed to 2026. It's not 1 year delayed as you suggest.
What does the "more than half of them can move 6+" mean? Six+ cores working out of 4+8?
Clocks. Cores make no sense in this context.
 

511

Diamond Member
Jul 12, 2024
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That's foundry readiness. Intel 3 products came out in late 2024. 18A was supposed to be late 2025 with Clearwater but got delayed to 2026. It's not 1 year delayed as you suggest.

Clocks. Cores make no sense in this context.
It can't be 6+ though otherwise they would be shouting through the roof
 

DavidC1

Platinum Member
Dec 29, 2023
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It can't be 6+ though otherwise they would be shouting through the roof
Why not? The pipeline is already set for TSMC. In 3-4 years it'll be legacy node.

What else do you think it means? 6+ cores makes NO sense.
 
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DavidC1

Platinum Member
Dec 29, 2023
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How can half be at 6+ and the best at 5+ if it is clocks? If 6+ is clocks, what does best are 5+ mean?
Cores make no sense either. So you are saying it's instead half of them can have 6 cores enabled and best can do more than 5 cores? How can the best of ANYTHING be LESS than not the best?! He probably missed a sentence there.

If you are talking about Pantherlake, it's 4 individual P cores with 2 quad clusters of E cores. It doesn't make sense in that regard either. Also cores can use redundancy. Clocks cannot.