Lapped my i7-3770K and there was zero improvement in operating temperatures!?

[oceanside]

Very interested to see what IDC comes up with to replace the paste TIM under the hood.

Toothpaste? Maybe some dentu-grip?

 

[BonzaiDuck]

with IB i have a feeling you will need to delid and add better paste and possibly sand down the IHS a bit to make the gap between die and IHS smaller to see the temp changes you would normally get by just lapping. Intel really screwed the guys who like to OC to the bitter edge with IB.

First, for Denithor:

The plot of duopolies and dominant firms thickens! That article was dated from 2008. I actually think it was later that the "correct" TjMax was made known for the Q6600, so that temperatures weren't over-reported at 10C in excess of what they really were! As I said in another thread, if I'd seen the correct temperatures when I first built my Q6600 system, I might have pushed it to a 3.4 Ghz over-clock. Truth be told, reviews of the B3-stepping (no less!) showed air-cooled over-clocks possible to 3.5+.

Rifter, not sure what you mean be thinning down the IHS. I have to think about that. But two layers of TIM -- one on top of the IHS and the other between the IHS and core -- do not help.

That's why I think something like Indigo Xtreme would make up for it. Since it mildly bonds with metal, it would have less thermal resistance than any TIM even if greater than a solder. It would be more like a solder. I've got to slip over to Graysky's thread, just to see if there are answers to my question dealing with this very same thing.

 

[soccerballtux]

you can model the thermodynamics of the materials as 'resistors' where the resistance is determined by the thermal conductivity of the material.

in a normal scenario you have lets say a 0.1k ohm solder joint in series with a 2k heat spreader. Let's say lapping improves the heat spreader conductivity by ~10%. your total series resistance drops from ~2.1k to 1.9k. IE 10% more joules can be transmitted through the material.
but in this scenario you have a 5k resistor (crappy thermal compound) in series with a 2k heat spreader. You lap the spreader, get the same 10% improvement, but it doesn't matter because it's a much smaller fraction of the total series thermal conductivity of the HS with the crummy thermal compound.

If I had to guess, that's what's going on.

 

[Rifter]

you can model the thermodynamics of the materials as 'resistors' where the resistance is determined by the thermal conductivity of the material.

in a normal scenario you have lets say a 0.1k ohm solder joint in series with a 2k heat spreader. Let's say lapping improves the heat spreader conductivity by ~10%. your total series resistance drops from ~2.1k to 1.9k. IE 10% more joules can be transmitted through the material.
but in this scenario you have a 5k resistor (crappy thermal compound) in series with a 2k heat spreader. You lap the spreader, get the same 10% improvement, but it doesn't matter because it's a much smaller fraction of the total series thermal conductivity of the HS with the crummy thermal compound.

If I had to guess, that's what's going on.

I agree, thats why i think you need to address the issues below the heatsink and below the IHS as i hinted at in my post.

 

[Rifter]

First, for Denithor:

The plot of duopolies and dominant firms thickens! That article was dated from 2008. I actually think it was later that the "correct" TjMax was made known for the Q6600, so that temperatures weren't over-reported at 10C in excess of what they really were! As I said in another thread, if I'd seen the correct temperatures when I first built my Q6600 system, I might have pushed it to a 3.4 Ghz over-clock. Truth be told, reviews of the B3-stepping (no less!) showed air-cooled over-clocks possible to 3.5+.

Rifter, not sure what you mean be thinning down the IHS. I have to think about that. But two layers of TIM -- one on top of the IHS and the other between the IHS and core -- do not help.

That's why I think something like Indigo Xtreme would make up for it. Since it mildly bonds with metal, it would have less thermal resistance than any TIM even if greater than a solder. It would be more like a solder. I've got to slip over to Graysky's thread, just to see if there are answers to my question dealing with this very same thing.

What i was suggesting is sanding some material off the bottom of the IHS so that when you reseat it onto the CPU it will make the gap beween the IHS and the CPU die smaller, which should theoretically improve thermal performance.

 

[Idontcare]

What i was suggesting is sanding some material off the bottom of the IHS so that when you reseat it onto the CPU it will make the gap beween the IHS and the CPU die smaller, which should theoretically improve thermal performance.

Yeah that's a great idea :thumbsup:

I just popped the lid and there is a distinct ridge of black adhesive that remains on the PCB portion of the CPU package as well as on the underside of the IHS itself.

I'm thinking that if I clean off the black adhesive alone, necessary just to ensure the IHS actually reseats level with the enclosed CPU silicon later on, then that will diminish the gap between the underside of the IHS and the top side of the silicon by a meaningful amount.

Using a micrometer, I measure a potential ~0.05mm gain in removing the glue from the PCB and another ~0.08mm gain to be had in removing the glue from the IHS. That's a healthy ~0.13mm decrease in the gap right there.

PCB measured in area without glue:

PCB measured in area with glue:

IHS measured in area without glue:

Beyond that of course we further polish down the standoff ring that the underside of the IHS forms where it mates with the PCB, exactly as you suggested in your post.

 

[BonzaiDuck]

Is the black adhesive solid, like plastic, or does it have a rubbery feel to it?

EDIT: I was just looking at Coollaboratory's Liquid Ultra. It is described as being more viscous. I was also thinking that the IC Diamond would be a good TIM replacement -- non-conductive, wouldn't flow, etc. Once it dries, it has a rubbery feel to it. I don't see how nano-diamond particles are going to do damage to the CPU die.

But you could use them in combination. Not knowing anything about whether conductors are exposed under the IHS -- and someone mentioned this approach before of making a "silicon grommet" for use with these metal pastes -- the diamond paste would be just as effective for that.

I also found an earlier thread -- IDC and others had contributed during the spring around May -- there were thoughts about expansion and contraction as a consideration for Intel's choice to use the thermal grease instead of the indium-silver solder. Those may be concerns, but it's equally likely that they may have wished to deliberately make the IB thermally limited. With the Liquid Ultra, it's going to flow a tad if it gets hot enough. So those other engineering concerns wouldn't apply.

Someone else speculated about the cost of doing it this way or that, eroding the unit margin. For the costs cited, I can't see how it would have an impact on product demand if they simply passed on the cost to the consumer -- either way it's an insignificant part of the cost and therefore the price.

 

[Plimogz]

I just popped the lid and there is a distinct ridge of black adhesive that remains on the PCB portion of the CPU package as well as on the underside of the IHS itself.

AMD chips were exactly like that for the longest time. Of course my experience is based on years ago, but has it changed so much? -- I haven't had the opportunity to open up a newer AMD part; did either maker recently sell chips which were so very different from this ?

While I realize that this isn't my $300 piece of silicon to risk, I wonder at all this talk of sanding the IHS and spreading on double layers of TIM. Sure I seem to recall reading something about smaller processes having thinner, more fragile substrates, and thus dies... But damnit, is it so far out of the question to just stick a nice, massive copper heatsink (or waterblock) on top of a naked IB die? Didn't we all go years clumsily clamping fat aluminum heatsinks onto naked dies not that long ago?

 

[graysky]

What i was suggesting is sanding some material off the bottom of the IHS so that when you reseat it onto the CPU it will make the gap beween the IHS and the CPU die smaller, which should theoretically improve thermal performance.

Wait... the die is a fixed distance off the PCB and the inside of the IHS is also a fixed distance, so by removing the intel black sealant of height x we are effectively lowering the internal clearance between the die and the IHS by that same distance. Am I thinking about this right?

 

[_Rick_]

Why use TIM if you lap - if you go for perfect flatness, as that mirror finish suggests, then just do the same to the base of the cooler, and slap it on. Voilà, perfect contact.

Only thing you would maybe want to apply is an anti-oxidative coating.
The nickel may be less thermally conductive, but it's what protects the copper from oxidation, which is probably accelerated at the temperatures it reaches, if not properly isolated from ambient oxygen.
Copper oxides are probably less ideal for thermal capabilities, will ruin the finish over time, and are generally not desirable.


But seriously, just dump the IHS, lap your heatsink, and mount that sucker on the die, with a breath of low viscosity, non-conducting thermal compound.

 

[Meghan54]

Why use TIM if you lap - if you go for perfect flatness, as that mirror finish suggests, then just do the same to the base of the cooler, and slap it on. Voilà, perfect contact.

A mirror finish doesn't equate to a surface devoid of all microscopic peaks and valleys, esp. with metal. That's one reason we use TIM.

 

[Rifter]

Wait... the die is a fixed distance off the PCB and the inside of the IHS is also a fixed distance, so by removing the intel black sealant of height x we are effectively lowering the internal clearance between the die and the IHS by that same distance. Am I thinking about this right?

Yes

 

[cantholdanymore]

, another IDC myth busting thread :thumbsup::thumbsup:

 

[_Rick_]

A mirror finish doesn't equate to a surface devoid of all microscopic peaks and valleys, esp. with metal. That's one reason we use TIM.

That does make lapping quite useless though.
If you'll be using TIM in any case, and don't try to achieve near-perfect contact, then you might as well not worry about the nickel plating and slight surface imperfections - the thermal interface material, and its two material boundaries are more likely to have an impact.

I guess if you were to use an especially liquid TIM that easily displaces and allows for lots of direct contact, while being dosable to the tiny amount required, then there could be a benefit. But a bit of pressure mounting should probably render the TIM useless anyway, as the two surfaces mold onto each other.

Someone with spare time should do some tests....or link me to existing results

 

[soccerballtux]

on the bright side you don't have to worry about killing the CPU now that it's thermal compound and not solder. So no real reason NOT to remove the IHS.

 

[Ferzerp]

Is the black adhesive solid, like plastic, or does it have a rubbery feel to it?

Since he hasn't answered yet, it's very rubbery.

 

[BonzaiDuck]

Since he hasn't answered yet, it's very rubbery.

Some folks seem to have grasped what I was suggesting with the question. Either way, it would seem that the cap was supposed to receive support around its edges. If the adhesive set to a hard substance, the manufacturer would've been confident the cap and die were sufficiently mated together for good contact and thermal transfer. Or, a flexible adhesive would still accomplish the same thing after it had set.

For the rest of it, I don't know what I have to do to convince others of what I know for myself -- resurrect my Excel files of thermal data from 2007, when I was testing the difference between the plated and unplated copper surfaces? Or for that matter, the difference between diamond paste and AS5?

Graysky noted in his thread that he didn't want to use a substance (like a gallium-indium alloy in liquid form) which would form a bond with the metal in either a heatsink-base or the IHS. I'm not sure -- if the processor die itself presents a silicon surface -- that it does any such thing with that side of the equation, but it would form a slight bond with the bottom of the processor cap.

In addition to the substances used for such TIM products, the bonding or amalgamation with the metal contact surfaces further improves heat transfer.

Just for experimental purposes -- to see how shoddy the Intel TIM really is or how they may have calculated it to be -- we already know the other mainstream products show improvements over some 5C degrees. Other forum posts elsewhere that I'd seen suggested up to a 20C improvement for the "liquid pro" substance. So ultimately, to me it only seems practical to pick the most effective TIM or interface possible for permanent use if you're going to the trouble to pull the IHS off the processor anyway.

The data on those products is available on the web, and had been cited by folks here in discussions from a year ago. The data on IC Diamond is also available, and I actually ran my own tests and reported them here back in '07. The nano-diamond is non-conductive, but it doesn't bond with the surfaces. After drying, it has a rubbery feel to it.

I just think the options being chosen, for all the trouble of removing the IHS, are not the best. Unless you plan on repetitively pulling the IHS off the processor, I'd think you'd want to skip using the less effective TIM replacements.

 

[dave_the_nerd]

Don't you have to run the machine for a bit before the thermal compound "breaks in?" Or is that outdated now?

 

[Ferzerp]

Well, pulling the IHS off repeatedly is simple because there's really no reason to permanently affix it once you have it removed. It's not going to fall off while you're mounting it (though it will shift around a bit so you have to place it properly). The adhesion of whatever TIM you use will keep it in place really well. As long as you use a reasonably adhesive TIM (which all the paste ones are).

 

[KingFatty]

Has anyone tried to solder the IHS onto the chip - or would that be insanity?

 

[BonzaiDuck]

Don't you have to run the machine for a bit before the thermal compound "breaks in?" Or is that outdated now?

That's mostly true for the AS5 compound. The IC Diamond doesn't "break in;" mostly, it dries out a bit. With the Indigo-Xtreme and other "pad" products, they have to reach a temperature of approximately 80 to 85C to reach a liquid or semi-liquid state, at which time there is some bonding or amalgamation with the other metal surfaces. Some people have used devices like hair-dryers focused on heatsink fins to make this happen. But with the Ivy Bridge, you'd mostly only need to load the processor briefly -- which you're going to do anyway to test stability.

With the products like Liquid-Ultra, they are already in paste form.

Has anyone tried to solder the IHS onto the chip - or would that be insanity?

I don't know anything about Intel's process other than the earlier generations used what is described as a "fluxless solder" of indium and silver. I wouldn't have the slightest idea of how they did it, or how it works. So I do think it would be insanity to use materials, methods or tools we use to make permanent wire electrical connections.

 

[Idontcare]

Is the black adhesive solid, like plastic, or does it have a rubbery feel to it?

EDIT: I was just looking at Coollaboratory's Liquid Ultra. It is described as being more viscous. I was also thinking that the IC Diamond would be a good TIM replacement -- non-conductive, wouldn't flow, etc. Once it dries, it has a rubbery feel to it. I don't see how nano-diamond particles are going to do damage to the CPU die.

But you could use them in combination. Not knowing anything about whether conductors are exposed under the IHS -- and someone mentioned this approach before of making a "silicon grommet" for use with these metal pastes -- the diamond paste would be just as effective for that.

I also found an earlier thread -- IDC and others had contributed during the spring around May -- there were thoughts about expansion and contraction as a consideration for Intel's choice to use the thermal grease instead of the indium-silver solder. Those may be concerns, but it's equally likely that they may have wished to deliberately make the IB thermally limited. With the Liquid Ultra, it's going to flow a tad if it gets hot enough. So those other engineering concerns wouldn't apply.

Someone else speculated about the cost of doing it this way or that, eroding the unit margin. For the costs cited, I can't see how it would have an impact on product demand if they simply passed on the cost to the consumer -- either way it's an insignificant part of the cost and therefore the price.

I don't buy the conspiracy theory angle. It would be self-defeating in all their other product segments and the tradeoff would not make any sense at all.

What percentage of IB chips are going to be sold to non-OC'ers? 98% of them? (including server market and notebooks)

Operating temperature impacts power-consumption, power-consumption is a big care-about in both the mobile and the server marketspaces.

There is no way that Intel's decision makers would elect to have their 22nm products underperform to their potential in both the notebook and server segments just so they could field thermally limited 3570k and 3770k chips to the desktop segment.

So the tradeoff in going with the non-solder TIM under the IHS definitely costs Intel lots of money in terms of lost revenue potential, all their server chips and mobile chips are going to be clocked lower and spec'ed to operate at a higher Vcc because of the resulting higher operating temps, and the decision to lose out on that revenue had to come on the heels of a serious trade-off being made that would have cost them even more money in the long run.

And the one thing that would have cost them more money in the long run is in-field fails that must be covered by warranty. No one wants that, the risk of it is one of the huge incentives that process engineers have in scaling existing solutions versus implementing brand new solutions like HKMG or 3D xtors.

We had a huge in-field fail issue at TI when we were the first to introduce a lower-k dielectric material into the BEOL (we used HSQ vs everyone else using SiO2 at the time) and we didn't enough testing to capture the reality of stress-induced cracking that would happen in the dielectric from thermal cycling. Thereafter we were keen to never repeat that mistake, it was extremely costly (hundreds of millions of dollars in warranty charges).

With Intel changing so much of the xtor structure at 22nm you can bet they did extensive/exhaustive internal testing to ensure the risks were fully identified and mitigated. It makes engineering and financial sense to conclude the shift in soldering the IHS to the CPU at 32nm to now just putting a nice malleable TIM at that interface at 22nm (at great expense in terms of lost revenue in all product segments) must have been done for stress and thermal-cycling reasons.

AMD chips were exactly like that for the longest time. Of course my experience is based on years ago, but has it changed so much? -- I haven't had the opportunity to open up a newer AMD part; did either maker recently sell chips which were so very different from this ?

While I realize that this isn't my $300 piece of silicon to risk, I wonder at all this talk of sanding the IHS and spreading on double layers of TIM. Sure I seem to recall reading something about smaller processes having thinner, more fragile substrates, and thus dies... But damnit, is it so far out of the question to just stick a nice, massive copper heatsink (or waterblock) on top of a naked IB die? Didn't we all go years clumsily clamping fat aluminum heatsinks onto naked dies not that long ago?

I did just that about a year ago with my GTX460 for fun. The trick of course is building the right standoffs so the die doesn't take the brunt of the mounting pressure, particularly so the pressure is even across the entire die.

This can be done with IB of course, the retention bracket on the mobo will have to be removed (shouldn't be an issue, it is bolted on so it can be unbolted).

From my experience with delidding my GTX460, I'm definitely going to at least attempt to do the same with my 3770k at some point in the tests.

 

[BonzaiDuck]

There is no way that Intel's decision makers would elect to have their 22nm products underperform to their potential in both the notebook and server segments just so they could field thermally limited 3570k and 3770k chips to the desktop segment.

So the tradeoff in going with the non-solder TIM under the IHS definitely costs Intel lots of money in terms of lost revenue potential, all their server chips and mobile chips are going to be clocked lower and spec'ed to operate at a higher Vcc because of the resulting higher operating temps, and the decision to lose out on that revenue had to come on the heels of a serious trade-off being made that would have cost them even more money in the long run.

And the one thing that would have cost them more money in the long run is in-field fails that must be covered by warranty. No one wants that, the risk of it is one of the huge incentives that process engineers have in scaling existing solutions versus implementing brand new solutions like HKMG or 3D xtors.

The argument about warranty makes more sense. What we're wondering is what risk they encountered in an established process applied to this new die-shrink, that would make them choose such a s***ty and ineffective alternative.

 

[AtenRa]

Has anyone tried to solder the IHS onto the chip - or would that be insanity?

Dont forget to put your safety mask when welding the IHS to the die :biggrin:

 

[sm625]

There is no way that Intel's decision makers would elect to have their 22nm products underperform to their potential in both the notebook and server segments just so they could field thermally limited 3570k and 3770k chips to the desktop segment.

How do you know notebook and server chips have the same problem? Has anybody delidded a notebook chip? Do we even have the dimensions of the IHS for the notebook chips?