NostaSeronx
Diamond Member
- Sep 18, 2011
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If it does come out to be 16KB, it could be that AMD decided to finally use 8T SRAM or 10T SRAM structures.That cannot be SR core since we now know 100% that SR-B core has 16KB dedicated L1 data caches. The module in this image was disected by Hans and a few other people and they stated the data cache structure looked doubled and was now 32KB per core.
From what I can gather the scheduler and retirement queue has been enhanced. For both the x86 cores and x86 FPU.Actually, I think Seronx's SR version would be less performing, cutting clocks in half in order to double almost everything in the Integrer/FPUs. Going 2x wide doesnt necesarily mean 2x IPC in real world scenarios.
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