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Kaby Lake information.

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Fjodor2001 said:
They can do variants both with and without HBM.

An APU with 4C/8T + HBM could be priced quite high and still be competitive, because it would compete with a separate CPU/APU + discrete GFX card which costs a lot.
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Sure it's technically possible, it's also expensive and money isn't something AMD is floating in.
 
mysticjbyrd said:
I am guessing a long time ago, but it's still not the same as planning something out from the start. Why do you think they are working on the IGPU right now?
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Kaby Lake contains core improvements too. Its a product begun a long time ago.

Remember, just because a company doesn't say there is issues to the public, doesn't mean they dont know it and haven't planned against it.
 
ShintaiDK said:
Kaby Lake contains core improvements too. Its a product begun a long time ago.

Remember, just because a company doesn't say there is issues to the public, doesn't mean they dont know it and haven't planned against it.
Click to expand...

I'm still wondering what the scope of these changes are from Skylake are. If they are too much, that means they knew from two years ago that 14nm was a real screw up and wouldn't be a quick fix, so I'm not betting too much on it.
 
ShintaiDK said:
There is a whole line that doesn't include the P4. Its called the Pentium-M.

If you exclude AMDs faildozer aka P4, you see the same case at AMD.
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We were not talking about AMD, we were talking you saying that the improvements over architecture after another being pretty much the same since PPro.
 
mysticjbyrd said:
It wasn't even really planned, until after they realized they couldn't meet the deadline for cannonlake. I wouldn't expect a heck of a lot outside of a slightly better igpu.
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Still, minor tweaks to core + what they did with devils canyon. If you get 400 mhz higher clocks, that would be already a lot.

I'm more interested in the platform though. Intel specifically stated support for Intel optane. These are products based on their and microns non-volatile 3D Xpoint memory. However it's unknown what it will actually support. if it is just ulra-fast SSD's or if it actually support RAM-sticks based on 3D Xpoint.

Just imagine you could use 2 RAM slots for RAM and the other 2 for non-volatile memory. That would be an insane speed increase over even fastest PCIe SSD.
 
ShintaiDK said:
You can start with this, that you may most likely reject. Dothan to Broadwell. 2003 to 2015.

intel-xeon-ipc-chart.jpg

http://www.nextplatform.com/2015/03/09/intel-crafts-broadwell-xeon-d-for-hyperscale/

Else some good information in this post:
http://forums.anandtech.com/showpost.php?p=37939597&postcount=106
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That chart is bollocks, at least for PC: http://www.tomshardware.com/charts/...based-values-added,Marque_fbrandx14,2779.html

Sandy Bridge had far greater gain than Nehalem. Nehalem only jumped out in situations where it had multi-threading advantage and memory bandwidth sensitivity. In RWT forums some people testing saw that those that are hard to parallelize programs Nehalem even shown regression.

Haswell vs Ivy Bridge 5-10% gain: http://www.pcper.com/reviews/Proces...irst-Enthusiasts/Clock-Clock-Skylake-Broadwel
Again: http://www.tomshardware.com/reviews/core-i7-4770k-haswell-performance,3461-5.html

http://www.anandtech.com/show/8426/...view-core-i7-5960x-i7-5930k-i7-5820k-tested/2
"Average results show an average 17% jump from Nehalem to SNB-E, 7% for SNB-E to IVB-E, and a final 6% from IVB-E to Haswell-E. This makes for a 31% (rounded) overall stretch in three generations."

All the tests show Sandy Bridge gain was better than Haswell, unlike Intel graph.

Rules for IPC comparisons:
-Same clocks
-Take out easy to optimize synthetic applications(like wPrime, Dhrystone, encryption)
-Are some of the programs too sensitive to one aspect of a chip? Like memory bandwidth. While BW is important, it doesn't reflect IPC of a chip
-Are we talking about server or PC?
 
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My guess is that Tick - Tock - Tock means now:
Tick = New arch,
Tock = The new arch + eDRAM
2nd Tock = Shrink of New arch, no eDRAM.

If they can play the shell game with HEDT being a year behind and eDRAM getting removed and added back in, they can always ensure there is something faster even with the pace of releases slowing.

Thus, I would not be surprised if Cannonlake ships with eDRAM SKUs. I don't think it will be eDRAM across the board though, probably only select SKUs.

The new 3D memory tech will be insanely cool when that lands. The bigger question is likely when will the actual memory hit in an affordable fashion, I think CPU support will happen before the actual memory will be on the scene in a big way.
 
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Headfoot said:
My guess is that Tick - Tock - Tock means now:
Tick = New arch,
Tock = The new arch + eDRAM
2nd Tock = Shrink of New arch, no eDRAM.
Click to expand...
Traditionally, at least, the whole "tick / tock" model was defined in terms of silicon process changes. So the "Tick" was the shrink, not the new arch.
 
Yea, to me, no matter how intel tries to spin it, the model now is tick, tick, tock. A new architecture, some tweaks (tick 1), a shrink(tick 2), and then a new architecture(tock).
 
frozentundra123456 said:
Yea, to me, no matter how intel tries to spin it, the model now is tick, tick, tock. A new architecture, some tweaks (tick 1), a shrink(tick 2), and then a new architecture(tock).
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Agree. We are seeing this way for everyone tho. GPus are already what, tick tick tick tock? 😉

Headfoot said:
My guess is that Tick - Tock - Tock means now:
Tick = New arch,
Tock = The new arch + eDRAM
2nd Tock = Shrink of New arch, no eDRAM.
Click to expand...

I dont believe in the add and remove of the eDRAM.
 
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Basically, each new arch gets eDRAM+GPU architecture increase (with IPC increase being less than 5%), a shrink, and deployment into HEDT in separate steps so that each architecture can go farther while still offering new products. (4 distinct implementations of the same base architecture, as opposed to the 3 of previous years)

IMO eDRAM+GPU architecture enhancements will form the "new" refresh step to switch from a 2 year architecture lifecyle to a 3 year architecture lifecycle, since the HEDT and Shrink strategies are already rolling.

There will be smaller updates, chipset stuff, video decode/encode enhancements, and the like. But I think that the main focus of of each release will follow along those lines. Shrinks will also likely increase GPU size without majorly changing architecture. GPU architecture + eDRAM changes will be the headline feature of the new "tick."

This is all speculation on my part of course, and not comprehensive of all the strategy. Just as to the differences between tick tock of yore and tick tick tock of tomorrow.

And I hope I'm wrong insofar that increasing core count becomes a regular feature too.
 
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Kaby Lake is a new lineup of desktop/mobile CPUs, not a couple of niche models like (desktop) Broadwell-K. New x86 core (rumoured) + improved graphics is way more substantial than a simple clock boost (Haswell Refresh). IMHO this was planned long before the 10nm delay became 'public'.
 
Too bad edram is still a very nich product, except for Apple. First we got soldered in chips, then the aborted broadwell K. Now there are a lot of skylake skus that supposedly will have it, but only available as an option in extremely expensive products. What i would like to see is iris pro standard on the quad i7 mobile chips. Intel gets a good price for them anyway, and something like that would seem to offer decent entry level gaming. Make the lowest discrete mobile card the 960m.
 
jpiniero said:
HDMI 2.0, updated video codecs and 3DXP support. Maybe you will get the wireless charging promised for Skylake.
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News from today at SweClockers:
http://www.sweclockers.com/nyhet/21588-intel-drojer-med-hdmi-2-0-till-cannonlake

Google-Translated to English:
https://translate.google.com/translate?sl=auto&tl=en&js=y&prev=_t&hl=en&ie=UTF-8&u=http%3A%2F%2Fwww.sweclockers.com%2Fnyhet%2F21588-intel-drojer-med-hdmi-2-0-till-cannonlake&edit-text=

Intel lingers with HDMI 2.0 to Cannon Lake
[...]
When Intel intends to give official support for HDMI 2.0 has hitherto been shrouded in mystery, but now can SweClockers reveal that it takes to Cannon Lake. Processor family who is expected to arrive no earlier than the end of 2017, succeeding Kaby Lake, which is expected to appear in the autumn in 2016.

Anyone who looked forward to HDMI 2.0 in Intel's integrated graphics parts can however avoid having to wait to Cannon Lake. The same source claims that Kaby Lake admittedly lacks native support for HDMI 2.0, but that it should be possible for manufacturers to add the extra circuitry in laptop computers. Whether this is also possible with motherboards designed stationary use is not clear.
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Kind of sad. I though it was primarily/only the iGPU that was supposed to get an improvement in KabyLake over Skylake. So I assumed it should include HDMI 2.0 since it has been around for a while now. Introducing it first in CannonLake is a bit late.
 
I saw mentions of Kaby Lake PCH in late 2014 in reference to the Basin Falls platform. I thought at the time Kaby Lake was just the name of the PCH but instead it turned out to mean "the same PCH that's used with the Kaby Lake processor."

Intel has been working on Kaby Lake for quite a while.
 
Anyone who looked forward to HDMI 2.0 in Intel's integrated graphics parts can however avoid having to wait to Cannon Lake. The same source claims that Kaby Lake admittedly lacks native support for HDMI 2.0, but that it should be possible for manufacturers to add the extra circuitry in laptop computers. Whether this is also possible with motherboards designed stationary use is not clear.
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Isn't that what they currently do with Skylake? I recall seeing some Motherboards (Gigabyte I think) that supported HDMI 2.0 with Skylake because they use an extra chip. Basically, nothing changes.
 
ShintaiDK said:
Agree. We are seeing this way for everyone tho. GPus are already what, tick tick tick tock? 😉



I dont believe in the add and remove of the eDRAM.
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I dont have any problem with tick, tick, tock. I just wish the tock brought a bit more improvement in absolute performance. The gpu "tock" should be huge. And, yes I know for gpu you can mostly just throw transistors at the problem.
 
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