Decreasing the operating voltage from 1V to 0.78V would be expected to reduce power-consumption by 50% if everything else was held constant (i.e. you reduced the voltage on a chip from the same node).
So we'd expect the lower-voltage chip to consume only 60% of the power that the higher-voltage chip consumes when both chips are clocked the same and produced on the same node.
The graph compare a 32nm planar with a 22nm trigate,
so this is a comparison between a 1V VDD 32nm with
a 0.78V VDD 22nm trigate.
So the 60% figure has relelevance to this comparison,
not a same node comparison..
However, decreasing the operating voltage AND shrinking the elements (a further reduction in capacitance) decreases power-consumption even further because the capacitance is also decreasing.
Shrink to 22nm is already included in the trigate intrinsical parameters,
displyed by the graph why the hell are you adding a further shrinking..??...
Reading the link you mention, it appears that :
Parasistic capacitances are not reduced over the ratio
that a simple shrink would have provided with planar tech.
Higher speed is primarly due to higher transconductance
of the Fets that allow to switch on/off the said capacitances faster,
as generaly, capacitance reduction by shrink is partly balanced
by lower transconductance of the shrinked Fets..
Also, seems that they reduced the Fets Vth ( gate source voltage
threshold for device conduction) that help the Fets being more
responsive.
All in all, i dont expect better than 30% power consumption
reduction at normal speeds.
It might be that Intel, extending its Thermal Budget concept
will use the low power modes reductions in TDP to allow
the CPU to overclock well beyond its rated max TDP,
average TDP over a defined time being the new TDP scheming..