Magic, no. Required, yes. And BK basically admitted it as such - they really should not have gone this dense without it.
That's what you are saying though. EUV doesn't change the fact that there are other problems associated with scaling further down.
Let's look at history of recent scaling.
Copper Interconnect: With 0.18u for AMD and 0.13u for Intel they moved to using copper interconnects. This is to reduce resistance which likely became problematic as circuits became smaller.
Hi-K dielectric:
The dielectric was a mere 1nm thick. Scaling that down allowed for performance improvements. Because 1nm was too small, they went with Hi-K materials, which allowed for a 3nm thickness(easier to manufacture) to be equal to a 1nm one. Now they could scale again.
FinFET/TriGate: Now people say node designations mean nothing, because it used to mean size of the gate, but gates are far larger. Well, Gate scaling stopped because it was too small. Gate scaling was also for performance. So they went with multiple gates, allowing them to keep the larger size while performance gains continued.
All it matters for density are pitch between the transistors, and pitch from one side of the transistor to the next. That's why more exotic materials are used, so they can keep the performance of a smaller traditional material while keeping the size larger(again to make it easier to manufacture).
You'll see for "10nm", every feature size of the transistor is larger than 10nm:
https://en.wikichip.org/wiki/10_nm_lithography_process
In general though, pitch scaling allows for density to scale. So the accusation about node designations meaning nothing is not painting the whole picture. Yes, to a purist its inaccurate, but for practical purposes not entirely wrong.
Transistor menus: We used to have one transistor type serving all markets. Now, you need a performance optimized one, and a density optimized one, and even a low power optimized one, at minimum. Chips now require 11-metal layers of various thickness, when back in 130nm/0.13u, Intel processes had only 6 layers. This is because circuits are getting more complicated, while process problems compound as it continues to shrink. Various layers serve as connections for different parts of circuitry. Some are performance optimized, some are for reducing leakage.
So, even if EUV works out well in practice, and it becomes next "pen" to print out small wires much easier, it does not solve the above problems that'll continue to compound the issues they have now. And the industry will not invest(at least at scale) if the advantages are minimal. At least, maybe the foundries will have a slightly easier time because they will move to 3nm(supposedly 7nm equivalent for Intel?) progressively(7 to 5 to 3) rather than do a huge jump as Intel is planning.