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Is Intel's upcoming 10nm 'launch' real or a PR stunt?

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maddie

Diamond Member
Jul 18, 2010
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I still think the overriding issue is they went too dense without EUV basically. Which to me says the issue might not ever be resolved.

Intel almost has to put 10nm into HVM at the end of next year at the latest unless it is completely unusable/ready to give up on it.
Some bold suppositions there.

As a what-if, what do you think is waiting if 10nm as presently constituted is unredeemable? We keep thinking that it's only a matter of time before 10nm CPUs are fully released, but you made me realize the potential error in that assumption.
 

jpiniero

Diamond Member
Oct 1, 2010
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Some bold suppositions there.

As a what-if, what do you think is waiting if 10nm as presently constituted is unredeemable? We keep thinking that it's only a matter of time before 10nm CPUs are fully released, but you made me realize the potential error in that assumption.
The most obvious would be to keep milking 14nm until their 7nm EUV is ready... the other would be to suck it up and port designs to TSMC. The problem of course is that one way or another the products they have in the pipeline for 7nm are dependent on 10nm being there one way or another, so they would have to do something about those too.
 

beginner99

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Jun 2, 2009
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The most obvious would be to keep milking 14nm until their 7nm EUV is ready... the other would be to suck it up and port designs to TSMC. The problem of course is that one way or another the products they have in the pipeline for 7nm are dependent on 10nm being there one way or another, so they would have to do something about those too.
They could backport? or is that that hard? At least for consumer chips they could just cut down on the iGPU to meet size limits but 14nm should be yielding that good by now even just making large dies should not be that huge of an issue.
 

IntelUser2000

Elite Member
Oct 14, 2003
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They can't just can 10nm and skip to 7nm. It doesn't work that way. These guys are at the top of the technology tree. It's like going to a place. You can ignore some details in the instructions to get there if you've already been there. Maybe someone else has. But if its a new place, if you skimp on the details you get lost.

Also, 10nm's problems have been commonly attributed to going too dense. With 7nm they want another 2.4x on top of that. They said with 10nm "they bit off more than they chew", and they want another 2.4x on TOP of that?

Technology advancements are progressive. Now the gains are coming really *hard*, which is why most others are taking smaller steps. Rather than going from 28nm to FinFET AND 2x density, they decided to move to "20nm", which focused on density, and then "14/16nm" which was focused on performance with FinFET. The future steps are similar. The 10nm, 7nm, the gains are much smaller than historical shrinks, in both performance and density. Little at a time, to reduce risks.

Intel decides to do the opposite, and do bigger jumps than before.
 

Lovec1990

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Feb 6, 2017
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I wonder then how can AMD do it last year they were on 14nm now they are on 12nm and next year they will be on 7nm how can much smaller company like AMD do it while intel cannot do 10nm?
 

Yotsugi

Golden Member
Oct 16, 2017
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I wonder then how can AMD do it last year they were on 14nm now they are on 12nm and next year they will be on 7nm how can much smaller company like AMD do it while intel cannot do 10nm?
Because Mark "Fabless model is collapsing" Bohr was wrong, and fabless model is more alive than ever.
 
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moinmoin

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Jun 1, 2017
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Because Mark "Fabless model is collapsing" Bohr was wrong, and fabless model is more alive than ever.
And it's actually pushing ahead like never before thanks to all the viable competition. Meanwhile Intel, not having been in competition with them for so long, had no sense of urgency at all and was fine with fine tuning 14nm without back ports, while continually chocking on the to-big-to-chew-on pieces they assembled for 10nm. A lot things went bad at once for Intel there.
 

Mopetar

Diamond Member
Jan 31, 2011
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I wonder then how can AMD do it last year they were on 14nm now they are on 12nm and next year they will be on 7nm how can much smaller company like AMD do it while intel cannot do 10nm?
The names given to different nodes are mainly marketing terms and have limited connection to how much they match reality, which is why Intel's 10 nm and TSMC/GF's 7 nm are quite similar under the microscope. Though 7 nm suggests that it should offer twice the density as 10 nm, I believe that Intel's 10 nm process has slightly higher density.

The 12 nm process that AMD is using is really just a tweaked version of the 14 nm process. Intel does similar things as well, but instead of choosing a new number, they call it 14++ rather than changing the number. However, it doesn't really matter as AMD shipping a 7nm part is going to mean they're on parity with Intel in terms of fab tech, which is an area where Intel previously always held an advantage.
 

jpiniero

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Oct 1, 2010
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Also, 10nm's problems have been commonly attributed to going too dense. With 7nm they want another 2.4x on top of that. They said with 10nm "they bit off more than they chew", and they want another 2.4x on TOP of that?
Because they are using EUV at 7 nm.
 

maddie

Diamond Member
Jul 18, 2010
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The names given to different nodes are mainly marketing terms and have limited connection to how much they match reality, which is why Intel's 10 nm and TSMC/GF's 7 nm are quite similar under the microscope. Though 7 nm suggests that it should offer twice the density as 10 nm, I believe that Intel's 10 nm process has slightly higher density.

The 12 nm process that AMD is using is really just a tweaked version of the 14 nm process. Intel does similar things as well, but instead of choosing a new number, they call it 14++ rather than changing the number. However, it doesn't really matter as AMD shipping a 7nm part is going to mean they're on parity with Intel in terms of fab tech, which is an area where Intel previously always held an advantage.
Is it correct to say parity in Fab tech?

The brutal truth is that it appears the 7nm nodes from TSMC and even GF are ahead of Intel's 10nm. Can you have a node, if you can't produce anything worthwhile on it? AMD making the claim that customers will be sampling Zen 2 later this year, sounds way ahead of Intel.

Combining this with a higher yielding small die MCM product and a new generation gets to see what hubris can pay.
 
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Despoiler

Golden Member
Nov 10, 2007
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Even if Intel's process is technically denser, faster, or lower power it doesn't matter if they don't have a process to release a product on. I think this is Intel biting off a piece they just can't chew. Intel admitted they were too aggressive with the process in an article I read. The other fabs have one thing they guarantee by not being the best at everything, consistent process availability. They don't have the option to have delays. They have huge customers waiting on their execution and those customers have their product execution tied to it. In the grand scheme of things the average consumer of the end device doesn't care about the details like we do. All they care about is that X company's marketing says it's better than the last generation. That's what competitors to Intel have been and continue to deliver.

I've said this before. Intel never made great chips. What they had was the best fabs in the world. That allowed them to jump to a new node anytime a competitor caught up to them. They were always a node ahead. That's why their chips were the best. Now that they don't have that advantage they are absolutely screwed.
 
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Mopetar

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Jan 31, 2011
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Is it correct to say parity in Fab tech?

The brutal truth is that it appears the 7nm nodes from TSMC and even GF are ahead of Intel's 10nm. Can you have a node, if you can't produce anything worthwhile on it? AMD making the claim that customers will be sampling Zen 2 later this year, sounds way ahead of Intel.

Combining this with a higher yielding small die MCM product and a new generation gets to see what hubris can pay.
That's a fair point. Having a technically inferior node that can yields loads of chips is far better than one that is only better on paper because you can't get product.

I still think that parity is a fair assessment simply because Intel's refined 14 nm process is actually quite good. Even Intel was projecting that the most recent refinement (14+++) will have better power/performance than 10 nm (not that it matters since they still can't produce chips on it) will in its first iteration. AMD using an MCM approach with Ryzen means that they'll be able to get more chips to market since a smaller die means more working CPUs, so it just squeezes Intel harder at the high end as they'll have much more difficulty making large monolithic dies to compete against the Threadripper and Epyc lines. Intel could still well old the single core advantage, but AMD probably won't care as they get the best market segments in terms of margins.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Because they are using EUV at 7 nm.
EUV isn't magic. With the amount of time EUV has been delayed, in a few years, they'll be using double patterning with EUV to print out circuits.

New technology takes time to learn and to be fully fleshed out.

I wonder then how can AMD do it last year they were on 14nm now they are on 12nm and next year they will be on 7nm how can much smaller company like AMD do it while intel cannot do 10nm?
If others have already blazed the path, then its easier for you to follow it. The mobile industry has already done its work on 10nm, and Global Foundries/IBM/Samsung do a lot of common work. Intel does their own, so 10nm is an entirely new path for them.

This is true for Intel too. They can "skip" 22nm and take their older chip(like some networking chips) on 32nm and go straight to 14nm, because 14nm is already well known and is a stable foundation.
 

jpiniero

Diamond Member
Oct 1, 2010
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The best part I think is that I don't think upper management was told that 10nm was in such serious trouble until roughly this time last year, as noted by BK's share selling.

There was a time where I thought that perhaps Intel had identified the issue properly and had adjusted their 10++ designs to actually fix the problems (meaning either inserting EUV or regressing on density to make it work) but that doesn't appear to have happened or didn't fix the issue.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Magic, no. Required, yes. And BK basically admitted it as such - they really should not have gone this dense without it.
That's what you are saying though. EUV doesn't change the fact that there are other problems associated with scaling further down.

Let's look at history of recent scaling.

Copper Interconnect: With 0.18u for AMD and 0.13u for Intel they moved to using copper interconnects. This is to reduce resistance which likely became problematic as circuits became smaller.

Hi-K dielectric:
The dielectric was a mere 1nm thick. Scaling that down allowed for performance improvements. Because 1nm was too small, they went with Hi-K materials, which allowed for a 3nm thickness(easier to manufacture) to be equal to a 1nm one. Now they could scale again.

FinFET/TriGate:
Now people say node designations mean nothing, because it used to mean size of the gate, but gates are far larger. Well, Gate scaling stopped because it was too small. Gate scaling was also for performance. So they went with multiple gates, allowing them to keep the larger size while performance gains continued.

All it matters for density are pitch between the transistors, and pitch from one side of the transistor to the next. That's why more exotic materials are used, so they can keep the performance of a smaller traditional material while keeping the size larger(again to make it easier to manufacture).

You'll see for "10nm", every feature size of the transistor is larger than 10nm: https://en.wikichip.org/wiki/10_nm_lithography_process

In general though, pitch scaling allows for density to scale. So the accusation about node designations meaning nothing is not painting the whole picture. Yes, to a purist its inaccurate, but for practical purposes not entirely wrong.

Transistor menus: We used to have one transistor type serving all markets. Now, you need a performance optimized one, and a density optimized one, and even a low power optimized one, at minimum. Chips now require 11-metal layers of various thickness, when back in 130nm/0.13u, Intel processes had only 6 layers. This is because circuits are getting more complicated, while process problems compound as it continues to shrink. Various layers serve as connections for different parts of circuitry. Some are performance optimized, some are for reducing leakage.

So, even if EUV works out well in practice, and it becomes next "pen" to print out small wires much easier, it does not solve the above problems that'll continue to compound the issues they have now. And the industry will not invest(at least at scale) if the advantages are minimal. At least, maybe the foundries will have a slightly easier time because they will move to 3nm(supposedly 7nm equivalent for Intel?) progressively(7 to 5 to 3) rather than do a huge jump as Intel is planning.
 
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