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Is Intel's upcoming 10nm 'launch' real or a PR stunt?

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LTC8K6 said:
And yet somehow we've known all along exactly what was going on with Intel and 10nm, every step of the way.

Amazing.
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Seems like everything we "knew" kept changing and continues to change at present. I can't understand how anyone can know anything if the situation is so fluid.
 
Mockingbird said:
You still don't "get it" or maybe you don't want to.

Intel just sent 10nm chips to OEMs and considered that a "launch".

Or as Brian Krzanich puts it, "The process works, we're shipping 10nm product today. So I did want to make sure that that was very clear to you".
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But I remember Intel saying they were shipping 10nm chips long ago...
“As we talked about before,” says Bryant, “we said we'd be shipping 10nm, codename Cannon Lake, parts just before the end of the year. We actually did that. So we started shipping our first 10nm, codename Cannon Lake, parts just before the end of the year and we're on schedule to be ramping throughout 2018, as we said previously.”
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That quote is from early January, claiming shipping had already begun in 2017.

So was the launch in 2017 then?

https://www.pcgamesn.com/intel-cannon-lake-launch-2017

Intel are launching 10nm chips before the end of the year, despite manufacturing hell
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Its PR. Their 10nm is so bad they are only using it on one mobile chip. I doubt they can have good yields before 2019.
 
i3-8121U isn't interesting, the m3-8114Y however is a real improvement over 5W parts on 14nm+ based on the base clock and comes with enabled iGPU. I wonder if we hear something about CNL-Y at Computex next week.
 
piesquared said:
Yes, of course it was launched. The product is on the market, therefore it was launched. Some people are just trying to redefine the term. Happens all the time. It was a silent launch, but a launch all the same.
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Yeah, we get it. The Challenger launch was a launch by some definition, but I don’t think anyone was happy with it.

Intel 10 nm hasn’t so much stumbled out of the gate as it has been pushed out to sputter around on wobbly legs.

However, what’s the alternative? Even if the best they can do is a low-end OEM chip, it’s better than throwing wafers away. Nothing wrong with salvaging as best as they can.

This the CPU/Overclocking forum.

This is not about NASA disasters. Keep it on topic.

AT Mod Usandthem
 
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Mopetar said:
Yeah, we get it. The Challenger launch was a launch by some definition, but I don’t think anyone was happy with it.

Intel 10 nm hasn’t so much stumbled out of the gate as it has been pushed out to sputter around on wobbly legs.

However, what’s the alternative? Even if the best they can do is a low-end OEM chip, it’s better than throwing wafers away. Nothing wrong with salvaging as best as they can.
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Are you serious man? I love to make fun of Intel fanboyism and naysayers as much as the next guy, but are you really comparing the launch of a new product to a fatal loss that took the lives of everyone on board? This is tasteless.

We don't allow that here.

AT Mod Usandthem
 
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Guru said:
Its PR. Their 10nm is so bad they are only using it on one mobile chip. I doubt they can have good yields before 2019.
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Intel announced that production ramp up would not be until 2019, so that was an easy doubt for you.
 
Some dude at Intel said today confirmed they are still going to release 10 nm FPGAs in 2019, be it high volume or not. So at the moment at least they are not giving up on 10 nm. Note that it is my understanding that FPGAs are very yieldable products so the defect rate doesn't hurt as much.
 
Is 10nm 'launched'? Yes, there is a product on the market with it. So technically this is correct. However, it's also clear this is a shareholder 'make happy' thing, with crappy clocks and limited availability. As others have said, a way to get at least something from crappy dies.
 
jpiniero said:
Some dude at Intel said today confirmed they are still going to release 10 nm FPGAs in 2019, be it high volume or not. So at the moment at least they are not giving up on 10 nm. Note that it is my understanding that FPGAs are very yieldable products so the defect rate doesn't hurt as much.
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"Some Dude" was Dan Macmara who is head of their PSG/Altera Group 😀
 
Why I feel that Atom will get the REAL 10 nm launch first and it will match SB performance by adding L3 cache?

Is that so... Intel, just release a board with PCI express with that Atom could be paired with a GT1030 or an RX 550 to make a new basic console machine.

That's because 10nm Core is lackluster and need a SB or Conroe jump.
 
jpiniero said:
Some dude at Intel said today confirmed they are still going to release 10 nm FPGAs in 2019, be it high volume or not. So at the moment at least they are not giving up on 10 nm. Note that it is my understanding that FPGAs are very yieldable products so the defect rate doesn't hurt as much.
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might be because fpgas are the easiest to produce.
 
maddie said:
Just read this on Real World Tech. Charlie's take on Intel's 10nm fiasco.

https://www.realworldtech.com/forum/?threadid=177250&curpostid=177250
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Nice read. Core issue according to the author:
If in what must have looked to some people at Intel as a touch of a genius you build a stack
- using metals with significantly different thermal expansion coefficients (16.5 for Cu vs 12-13 for Co),
- and one of them being brittle and having 4x worse thermal conductivity on top making hot spots even hotter,
how in the world are you going to fix that?!
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A 105c junction temp on a low watt chip is not unusual for Intel, though.
The 8121u also supports AVX512 and more PCIE lanes than the 8130u. Maybe those cause a higher junction temp. Several commenters seem to think the higher junction temp is actually good.
 
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LTC8K6 said:
A 105c junction temp on a low watt chip is not unusual for Intel, though.
The 8121u also supports AVX512 and more PCIE lanes than the 8130u. Maybe those cause a higher junction temp. Several commenters seem to think the higher junction temp is actually good.
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You did see the part about the quite dissimilar CoTE of the two metals? What happens when the temp delta increases, especially with one non-ductile?

I might have a PRO position opening soon.
 
maddie said:
You did see the part about the quite dissimilar CoTE of the two metals? What happens when the temp delta increases, especially with one non-ductile?

I might have a PRO position opening soon.
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People actually think Intel doesn't know that sort of thing?

What did the designer say? "Oops, I missed that in junior high science class? Sorry."
 
LTC8K6 said:
People actually think Intel doesn't know that sort of thing?

What did the designer say? "Oops, I missed that in junior high science class? Sorry."
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Sorry. You're absolutely correct.

Intel made the perfect choices and we're seeing the benefits of those presently. Silly me.
 
LTC8K6 said:
People actually think Intel doesn't know that sort of thing?

What did the designer say? "Oops, I missed that in junior high science class? Sorry."
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It's pretty clear that they dropped the ball somewhere. Maybe it's not the specific manner that was brought up in the linked post, but Intel doesn't have a process this far behind schedule without something being seriously wrong.

Sometimes even really smart people get caught up in looking at one aspect of a thing, or chasing something that appears to have a lot of promise or a major upside that they end up missing something important. History is rife with such incidents and its often only in hindsight that "any fool could see" the mistake.
 
LTC8K6 said:
People actually think Intel doesn't know that sort of thing?

What did the designer say? "Oops, I missed that in junior high science class? Sorry."
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Well, you can always count on Charlie for a reasoned, unemotional analysis (and for the usual suspects is these forums to pounce on it). It is really easy for someone who doesnt actually have to do the work and make the decisions to write scathing criticism, especially in hindsight. At this point though, I actually think intel would benefit from being transparent about what really happened, without giving away too much. Obviously, they made a poor choice somewhere, and also I would assume there was some reason that choice was made. I think the reasonable observer would probably be more forgiving of the delays if Intel actually said what they were trying to accomplish and what went wrong.
 
Mopetar said:
It's pretty clear that they dropped the ball somewhere. Maybe it's not the specific manner that was brought up in the linked post, but Intel doesn't have a process this far behind schedule without something being seriously wrong.
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I still think the overriding issue is they went too dense without EUV basically. Which to me says the issue might not ever be resolved.

Intel almost has to put 10nm into HVM at the end of next year at the latest unless it is completely unusable/ready to give up on it.
 
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