I disagree...while the process node gotchas are still ahead for AMD, most of the architectual gotchas are behind them (and rather painfully so!) for K10.
For Intel, the case is reversed...
I disagree...while the process node gotchas are still ahead for AMD, most of the architectual gotchas are behind them (and rather painfully so!) for K10.
For Intel, the case is reversed...
I am 100% ONLY talking about process tech, as this was Jackyp's position (for which I am attempting to clarify why its a valid position).
Not saying anything in my posts about the relative merits of whether mature process tech vs. mature architecture is better or worse in this race.
I am in no way implying that Nehalem is cheaper to produce (costs per die). I just stated they are similar in size and listed some of the possible advantages and disadvantages of each, updated the list with some more.
I am quite sure Nehalem will be expensive per die, but this could be offset by it's performance (IPC for a specific task), which would allow very low clocked (i.e. cheaper due to binning) chips to compete with high-end Shanghai and even higher-performing parts could then sell for a premium (if anyone is willing to pay that premium in those rough times that is). This totally depends on the tasks at hand, though.
Additionally Intel's economies of scale should affect profitability, but that has nothing to do with the chips per se.
Thank you for clearing up that immersion part guys, I was not aware of the different trade-offs it involved.
@viditor
However, I believe that we have enough data to more or less accurately predict desktop and workstation performance. We see that cache-loving applications get close to the promised 20% IPC gains, whereas others can be closer to 0%.
Compilation of more or less credible reviews and previews that are available: http://www.xtremesystems.org/F...howthread.php?t=209491
BTW techreport showed encoding, folding and rendering performance, a mainstay in their and anandtech's "desktop" reviews, because "power users" often do many "workstation level tasks" I think it's significant.
Phynaz
Lifer
- Mar 13, 2006
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Yes, I'm talking x86. We have never brought Itanium into our shop.
I can't get into specifics of course, but in data center type workloads - let's say if somebody were to see what a multi socket i7 performed like, they would certainly be taking another look at their '09 and '10 procurement plans.
Having seen the performance, such organizations would certainly ask the question "does this app need to run on Power?". Of course corporate politics would play a large role in the answer to that question.
Since I posted this in probably the wrong thread, I will repost it here (In probably the right thread.)
Since the AM3 3.0GHz Phenom 2 has a TDP of 95W, I wanted to calculate what frequency would bring the TDP to 125W - thereby estimating what future high speed binned parts might be made available.
Using relative scaling of dynamic power consumption (Thanks Idontcare), we can calculate what the higher binned parts may be for the AM3 model:
P = A*C*f*V^2
Assuming a 3.0GHz Deneb at 1.35V has an ACP of 95W
We get an A*C of 17.375.
Assuming this A*C holds true while scaling the CMOS to the temps and voltages under consideration:
The frequency at 125W calculates to 3.95GHz! So maybe we will see higher binned parts later next year.
Since the AM3 3.0GHz Phenom 2 has a TDP of 95W, I wanted to calculate what frequency would bring the TDP to 125W - thereby estimating what future high speed binned parts might be made available.
Using relative scaling of dynamic power consumption (Thanks Idontcare), we can calculate what the higher binned parts may be for the AM3 model:
P = A*C*f*V^2
Assuming a 3.0GHz Deneb at 1.35V has an ACP of 95W
We get an A*C of 17.375.
Assuming this A*C holds true while scaling the CMOS to the temps and voltages under consideration:
The frequency at 125W calculates to 3.95GHz! So maybe we will see higher binned parts later next year.
Did you account for any increase in voltage that might be necessary in going from 3GHz to 3.95GHz?
That might be what is holding AMD back a tad, if they need 1.45V or 1.5V to hit 4GHz then the ACP for such a part may break the budget.
I forget who but someone mentioned another potential reason for AMD not wanting to go there (4GHz) on retail SKU's just yet is that they probably factor in that Intel could do it just as well and so AMD won't accomplish much other than a short-term GHz race that results in increasing everyone's (Intel and AMD) cost structure to reliably yield 4GHz chips.
AMD may be biding their time until they have more confidence that creating a 3.5-4GHz SKU will still be viable at the equilibrium price-point after Intel counters.
I thought Nehlaem was out and about, info was free to spread? Is multisocket stuff still under NDA?
*edit - And having seen scaling between cores from IDC, I guess I'm missing something in what is so special about multi socket scaling. Assuming Denab has enough IPC, it should scale pretty well and perform well overall in multi socket configs...? I mean, that is on of AMD's strong points now, and with updated HT I would imagine it'll stay a strong point.
No. I was making an assumption that they would leave their voltage the same and just bin parts that could clock higher at that voltage. (I kind of doubt they will increase voltage requirements on stock CPU's as that is the voltage they have been designing chips to for years now.) I was trying to see what would happen if the TDP barrier was removed, but was not taking other variables into account. I truly don't believe that AMD will start selling 4GHz processors anytime soon, but seeing that power constraints are removed with AM3 CPU's, they may be able to move past 3.0GHz.
I don't doubt that they aren't getting into a clockspeed race because it would cut into their margins, but this gives me some hope that they may be able to in the near future if they feel that is in their best interest. Of course there are many other things that could keep them from releasing higher binned parts that neither of us has mentioned.
I just found it interesting at how high the frequency was when I did that calculation, and thought I would share. I expected it to be in the mid 3GHz range, not 4GHz!
Only the bloomfield (desktop LGA1366 i7) stuff is released and non-NDA. All the LGA1156 lynnfield/havendale as well as the xeon-line of nehalem stuff (gainestown) is still NDA.
Also please remember the scaling results from my analyses are from just two science applications, not really a broad-range of server type apps.
And scaling does not account for raw performance, its just another factor in determining how many cores need to be under the hood to hit a performance target...which then sets the price, margins, and power consumption. Think of it like IPC vs. GHz. You need both to determine absolute performance for a system. So to with scaling, it alone does not tell the whole story.
Yeah I understand the logic you are using, was just curious as I was too lazy to work thru the your math to answer my own question.
Just running the numbers, solving for max frequency while fixing ACP =125W and Vcc as a paremeter I get:
For Vcc of 1.4V we could see PhII at 3.67GHz and 125W ACP.
For Vcc of 1.45V we could see PhII at 3.4GHz and 125W ACP.
So even for worst case scenario being that AMD must feed lots of volts to bin chips at 3.4GHz they could potentially still fit into a 125W ACP envelope.
They've officially garnered my attention. Looking forward to Jan 8.
I understand that... guess from what little I've seen, even in a perfect world with 100% scaling I don't see what will be that incredible, but then again I don't know how well Shanghai scales in comparrison. But yea, I know scaling is just one piece of the puzzle, given the Intel IPC advantage it hardly needs 'great' scaling to compete. I guess I'll just have to wait for the NDA to be up.
*edit again - I suppose I should go look at some 4+ socket systems scaling to get a better idea how how well Nehlaem does when the NDA is up. I was under the impression that current AMD stuff scaled very well, well enough for Barcelona to equal/best Xeon in 4 and 8 socket systems even... but that was just from memory, and could be wrong.
They've earned it I guess, but just to play devil's advocate. Your calculations are based on the unofficial (?) TDP of an unreleased AMD CPU on an unreleased socket/platform targeting a june'09 launch, right? Those are many variables that could yield a mid 3ghz part in Q3'09, close to someone else's 32nm launch (-> just speculating).
I don't know if those numbers apply to all workloads. What do you say IDC?
The only problem is that Deneb (even though, we're talking about Shanghai in this case) won't have sufficient IPC on many workloads, this is fact (shown by Anandtech, Techreport, SPEC, etc. [1]) It may compete on those workloads where it is close IPC-wise, we just need to find out which ones e.g. Linpack does not look that bad for Shanghai.
AM3 being a new platform could face the same problems that nehalem will face for server upgrades (economy), if it won't be superior, it will be very hard to gain any kind of marketshare with that socket?
1. http://www.xtremesystems.org/F...howthread.php?t=209491
Oh yeah, it's a house of cards (er, speculation) we've built here, no doubt about it.
Not the same as pure fantasy as we've at least adhered to playing inside the limits of letting physics define the "what if" envelope for potential futures.
Nevertheless it is enjoyable to see what can be true if we take a few current speculations as facts. Although doing this when the 30k 3dmark numbers were rolling around would have led us down quite a proverbial rabbit hole too!
Yeah check my post to slowspyder above, there is a big caveat to those scaling results. Relevant for only the two applications tested by the reviewer. Wish I had an i7 then I'd test a few more desktop applications.
Heh heh. You are easily forgiven as your join date wasn't that long ago but this is one of Slowspyder's quirks if you will, he loves calling deneb as denab. Don't worry I am sure he knows he is intentionally mispelling it. It always makes me think of Donovan McNabb when I read it.
Denab...danab...the nab...the nabster....nabba rabba ding dabba, the nabba! :music: Denab!
This is a very vague statement, and I am confused why you would link it with the words "this is fact." What exactly is fact? What are these workloads and to whom would they be insufficient?
I don't doubt that Shanghai has inferior IPC in some applications to Xeon processors, but you don't exactly support your claim that they are. You reference links to a thread that you started on another board, and is just an amalgam of reviews and previews for Shanghai. Even reading through them, I don't see anything showing major IPC disadvantages to Xeon processors. Maybe I am missing something? (I don't have time to go through them all in depth right now.)
EDIT: I am not trying to berate you, I am just trying to get some clarification. I will be honest that some of these arguments are confusing me.
I'd like to take your way out and say I know I was mispelling it, but I didn't.
I guess I didn't pay much attention to it's name in the tech stories and that's just how it was in my mind. Opps! I knoo hwo 2 spel Fenom Denab reel goodd.
Well the SPEC numbers published on spec.org and discussed at RWT show it to be superior in bandwidth heavy _rates, where K10 and K10.5 normally could rule against penryns. Over at techreport they wrote that even their 1P nehalem (I know it was differently configured) outperformed 2P Shanghai and Penryn in quite a lot benchmarks and they hinted at the power of nehalem many times in the article, I think it's even in their conclusion.
It.Anandtech showed Nehalem to be faster at Linpack.
Many reviews show even Penryn outperforming Shanghai in int workloads (e.g. sunguard ACR, spec_int, spec_int_rate; SPECjvm2008 <- similar performance).
Nehalem improves performance in those applications yet again. So nehalem seems to be faster in most (or at least a lot) of the benchmarks where K10/K10.5 used to rule. The rest is just an extrapolation, as nehalem is based on core 2 and shanghai on deneb and core 2 used to be better in most other applications...
The early leaks of desktop Deneb showed it to be ~5% faster than K10 (linked in my thread), not a single rumour or leak showed Deneb to be considerably faster than Penryn (even though those tend to hype up the products), additionally there's the rule 'a die shrink cannot magically improve your architecture by 15-20%'.
Thus "Shanghai won't have sufficient IPC on many workloads" can be supported as a fact.
You could have found that out yourself going to all the links I posted and read =)
Now I see the interesting tidbits are few and in between and maybe not that easy to find?
...
...
*must stop constantly editing posts* edit #7
The techreport reviews of late are some of the better reviews I have read in their efforts to parse thru the multi-threaded capabilities and determine where the strengths are for a given architecture. I really look forward to them doing more CPU/platform reviews of deneb and gainestown.
Having said that, the Anand blog/review of Nehalem where he documented the system-level power consumption per benchmark (thus enabling true(er) computation of performance/watt) was stellar and I can only hope he continues going this extra mile and maybe the work ethic rubs off on some other reviewers out there as well.
Assuming this is true and without question, then the next question would be "is the IPC close enough that price can make the difference?".
i7 Xeon (i9?) may rule the roost but if AMD cuts prices on their shanghai processors to compensate for performance/cost (which arguably can/is always happen(ing)) then does AMD still make enough money to justify throwing R&D dollars into 32nm to chase Intel further and further down the rabbit hole?
There comes a point where the IPC deficit is not tenable going forward, just look at all the risc players that Itanium put to bed.
Perfectionism is preferred around here. You do your part to minimize the chances of miscommunication and we'll continue doing our part of insisting you don't know what you are talking about
On page 3, there was some confusion about the influence of process vs architecture on yields. I think it's an interesting issue worth some discussion.
Based on my limited understanding of semi manufacturing I'd assume there are two types of defects affecting yields (not talking about packaging & co affecting overall cost-structure or yields), those inherent to your silicon wafers and those caused by your tools. All defects are stochastic in nature and you can hardly influence where they occur.
The better - the more mature - your toolset the less errors it will produce. That's why we talk about "mature process" producing good yields.
But can architecture influence yields? Is there an influence apart from cache:core ratio? I guess so, but how important is it and why?
A. If your new architecture requires some changes to the manufacturing process, esp. changes in materials used. This will likely introduce new variables and could alter the characteristics of the process. For instance Nehalem's power gate, or even slightly changing the composition of your silicon?
I think a new architecture always requires some changes to the process - or at least they are regularly employed to produce an advantage (e.g. lower power at the same performance).
B. If error rates are inherent to the features used and particular types of transistors are easier to corrupt, architectural design choices could affect yields, assuming the overall balance of transistors is affected.
Which would be especially interesting in the case of Nehalem, because Intel has switched to mostly static CMOS, resulting in a completely different mix of transistors.
1. http://www.anandtech.com/cpuch...owdoc.aspx?i=3382&p=12
Yep that's the key question. I'm positive Shanghai will be slower than Nehalem-server, but Nehalem is probably more expensive both per die and as a platform, draws a lot of power and is the second iteration of Intel's 45nm process. If Intel does not royally screw up, it will outperform Shanghai (on average). How much? Let me ask my crystal ball...
Personally I believe AMD will need to target some niche markets, where they will be able to compete on price/performance, with Shanghai as soon as Nehalem ramps up. For instance system upgrades, virtualisation (if they're really performing that well in this big "niche"), low end, low power servers (if Intel does not launch ~2ghz nehalem parts), etc.
I'm still not quite sure whether the recent foundry spinoff is going to affect AMD in a positive or negative way? I'd venture the Arabian investors enable AMD to weather the storm and hope to somehow make money with the foundry, one day... Just how long are they going to wait for profitability?
BTW any news about tukwilla?
Haha. Yeah... At least we can have some kind of discussion without threads getting locked *hints at other places*
Perfectionism is preferred around here. You do your part to minimize the chances of miscommunication and we'll continue doing our part of insisting you don't know what you are talking about
The short-asnwer is that yes anything and everything can effect yields. There is simply no shortage of means and methods by which materials can interact to create undesired results. Architecture means layout which means geometry of the materials.
Galvanic corrosion for instance of metal-gates and/or copper-lines depends critically on the local layout of n and p xtors as they are exposed to oxidizing environments that water with dissolved oxygen pose.
Likewise layout geometries of anything conducting (gates, copper lines) produces an antenna structure which couples to the EMF of plasma-based processing tools (etch, deposition, etc) and can degrade the gate oxide in local regions on the die.
Architecture (layout) couples with process technology to generate new classes of defects all the time. Process gets tweaked to minimize the magnitude/quantity of these defects if/when it can be done, layout gets tweaked (called design rules) to accommodate new requirements to minimize the magnitude/quantity of these defects as well.
Defects are not always stochastic. There are systematic defects too. I won't get into it here as this post is already getting long. Needless to say the chemistry involved in self-assembly also occurs to form defects in systematic fashion. Resist poisoning for instance can be such that you get the same via on a die always being partially or fully blocked during etch by so-called poisoned resist (the acid catalyst generators end up being neutralized by mobile bases such as amines, NH4, in the stack). Fall-on defects tend to be stochastic, although where they "stick" versus where they don't stick depends on the surface chemistry and that depends on layout too. Needless to say there is good reason cmos R&D teams are populated with ranks of PhD's in chemistry and physics. It is rocket science at work in those fabs.
During my tenure at Texas Instruments I got to watch first-hand the transition from 100% in-house CMOS development and production to the current near-100% foundry outsourcing of CMOS development and production.
Based on this experience I say it's absolutely the best thing for AMD to make this transition. It is disruptive, things will be delayed/impacted by the shift as management focus is diluted by this activity as well as employee morale and sense of job security is undermined during such times. But looking out to 22nm and 16nm, TFC is AMD's only chance for competing with Intel's R&D budget on a timeline (node cadence) that Intel gets to set for this part of the industry (MPU's).
SUN made this transition from the start of their business model (starting with moto chips, then TI was the foundry for SUN up thru 65nm, TSMC is their foundry for 45nm and beyond at the moment) and it enabled them to compete against the likes of IBM and Intel in the big-iron markets for nearly 25 yrs now.
It might not be enough is the only thing. It was a necessary move due to financials of developing and manufacturing successive node shrinks. But will TFC be large enough to survive as well? They got to steal a lot of business from TSMC and UMC to get there. If they managed to get the SUN contract for say 22nm then that would be a massive boost to their coffers.
http://www.pcper.com/article.php?aid=534
I haven't heard much recently about tukwilla. It was supposed to launch this quarter, but it hasn't to my knowledge.
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