Interesting dispute brewing between Intel/TSMC

[Abwx]

My knowledge of this is shaky at best, but I think that they use a logarithmic scale in order to produce a linear graph for relationships that actually are exponential.

That s a by product , actualy a log scale is needed otherwise
the lower values would be all compressed in a tiny part of the
graph bottom , the log scale will magnify this part of the curve,
a good exemple below with the Fourier transform of a sinusoidal
signal , we can see the fundamental at 1khz and the first harmonic
at 2khz wich is 30 times lower than the fundamental , without the log
scale this first harmonic would do 1/30 of the graph height and would
be invisible , other harmonics would be litteraly stuck to the X axys.

For the record the two circuits are basic low level amplifier , the red one
use a bipolar transistor while the blue one use a field effect transistor
wich has the same principle as the transistors used in CPUs.

 

[Khato]

Apparently nobody understands logarithmic scales, it's just like quantum mechanics.

Wouldn't say that nobody understands them, just that most don't because they never deal with them. It's appropriate for use when talking about process density since scaling occurs in two dimensions, which is to say that ideal scaling from 22nm to 14nm would be 14^2/22^2. So by using a logarithmic scale you get a roughly straight line rather than a curve. (Which is exactly what you're saying at the end 🙂)

A logarithmic scale requires to know the actual numbers, because the scales are tricky, in their quality of being non linear. The following picture shows how the same difference of 1 can be a lot or very little.

Not really. It's actually a very nice system for doing relative comparisons since a certain distance on a log scale will always be the exact same percentage change. (On that picture of yours, take a look at the values if you recursively take 80% of 10, which is to say log(10) is 1, log(8) is roughly 0.9, log(6.4) is roughly 0.8, log(5.12) is roughly 0.7...) So if you wanted to you could find the percentage difference in density between TSMC 28nm and Intel 32nm in order to get your scale and from there be able to determine how everything relates.

 

[witeken]

Probably is the right term but with a 1/10 000 000 probability expectation..

Intel claims Q4 2015. They're already designing 10nm chips. TSMC expects to do that in Q4 2015.

 

[know of fence]

[...] It's actually a very nice system for doing relative comparisons since a certain distance on a log scale will always be the exact same percentage change.

Your replies and explanations are appreciated, without having run the numbers I didn't imagine that area would actually shrink to one tenth going from 32 to 10 nm.
Trying to wrap my mind around this, I actually managed to replicate the TSMC graph, by simply plotting the area [nm²] on a log-scale.

The kink you see in it at 16 nm is no reflection of any semiconductor qualities, or of TSMC's nefarious moving of percentages. It's just a consequence of not actually using a proper scale on the X-axis (most obvious impropriety being that 32/28 datapoints are on top of each other).

Now Intel were trying to communicate something when they showed that going from 20 nm to 16 nm FinFets the area remained unchanged. According to TSMC's graph this isn't true at all.

The screenshot shows both graphs in comparison, as well as a third graph based on nm-numbers, assuming "22 nm" isn't just a label but an actual pitch/distance of some sort.

 

[ShintaiDK]

Remember TSMC 10nm might actually end up being the real 14/16nm.

 

[Exophase]

Remember TSMC 10nm might actually end up being the real 14/16nm.

Not according to TSMC.

 

[Abwx]

Remember TSMC 10nm might actually end up being the real 14/16nm.

Do you realize that Intel s 14/16nm is done using
tools whose precision is 18nm at best..??..

 

[Nothingness]

What is funny is that on their slide Intel qualify their own 14nm number as forecast. For a slide from last November that's embarrassing :biggrin:

 

[ShintaiDK]

What is funny is that on their slide Intel qualify their own 14nm number as forecast. For a slide from last November that's embarrassing :biggrin:

Until an actual product is released. It will still be a forecast.

 

[Homeles]

Until an actual product is released. It will still be a forecast.

Really, it's until they decide to go public with their 14nm process data. They could release Broadwell but not disclose their process specifications. The specifications for the past couple of nodes were released before the products launched, I believe. Intel's keeping 14nm under wraps, among many other things at the moment.

 

[witeken]

Not according to TSMC.

But according to common logic? TSMC replace their planar 20nm transistors with FinFETs and call it 16nm. Then they do a shrink and call it 10nm. They're just exploiting the mess node naming has become: it doesn't give any useful information anymore except it's a big improvement from the previous node. My guess is that they try to hide their growing disadvantage against Intel.

 

[Khato]

Do you realize that Intel s 14/16nm is done using
tools whose precision is 18nm at best..??..

Oh? And how exactly did you come to such a specific conclusion regarding the limit on precision?

 

[Khato]

Your replies and explanations are appreciated, without having run the numbers I didn't imagine that area would actually shrink to one tenth going from 32 to 10 nm.
Trying to wrap my mind around this, I actually managed to replicate the TSMC graph, by simply plotting the area [nm²] on a log-scale.

Yeah, actually running the numbers and playing around with a logarithmic graph is definitely the best way to make sense of them 🙂 But simply taking the 'ideal' scaling from the process node labels ends up being nothing more than an academic exercise since they're only rough indications. For example, Intel's SRAM size (the only density metric that's usually offered as it usually demonstrates the best case scaling) went from 0.171um^2 to 0.092um^2 on the 32nm -> 22nm transition for a scaling of 1.85x, but the 'ideal' scaling for 32nm -> 22nm of 32^2/22^2 is 2.11x.

The kink you see in it at 16 nm is no reflection of any semiconductor qualities, or of TSMC's nefarious moving of percentages. It's just a consequence of not actually using a proper scale on the X-axis (most obvious impropriety being that 32/28 datapoints are on top of each other).

Now Intel were trying to communicate something when they showed that going from 20 nm to 16 nm FinFets the area remained unchanged. According to TSMC's graph this isn't true at all.

The screenshot shows both graphs in comparison, as well as a third graph based on nm-numbers, assuming "22 nm" isn't just a label but an actual pitch/distance of some sort.

Which is an incorrect assumption, same as all of the other node labels. But your chart actually does bring up a very interesting point - did TSMC simply change their line on the chart to correspond to the node label scaling rather than actual data? Because the similarities certainly make it appear as though such may be the case.

 

[know of fence]

... actualy a log scale is needed otherwise
the lower values would be all compressed in a tiny part of the
graph bottom, the log scale will magnify this part of the curve [...].

This definitely applies here somewhat, though we are dealing with just one order of magnitude.
Also I have to correct myself, Y = log(X²) is obviously not a straight, though it's somewhat straighter than the curve for theoretical area scaling, which is just a normal parabola Y = X².

My other take away from this whole debate is this:

Ideally both companies regardless of their choice of node would find themselves on the very same theoretical area scaling curve. Yet, Intel slides draw two curves, which is intentionally misleading. Moreover they present the crossing of the curves, an immediate consequence of comparing 2 different graphs with 2 different X-achses, as some kind of turning point/ breaking point for TSMCs progress.

 

[GreenChile]

Ideally both companies regardless of their choice of node would find themselves on the very same theoretical area scaling curve. Yet, Intel slides draw two curves, which is intentionally misleading. Moreover they present the crossing of the curves, an immediate consequence of comparing 2 different graphs with 2 different X-achses, as some kind of turning point/ breaking point for TSMCs progress.

I disagree. Nothing in Intel's slide is misleading from what I can tell. Intel was comparing the actual transistor density between the two companies at the nodes specified. This is a perfectly valid comparison. TSMC's chart is the one that is somewhat misleading because they are convoluting the results with other metrics (i.e. improved layout) which does not actually represent what the Intel was showing. I don't blame TSMC because the chart does show them in a poor light but the comparison of actual transistor density is properly displayed in Intel's slide.

 

[Phynaz]

Oh? And how exactly did you come to such a specific conclusion regarding the limit on precision?

Actually it's true in a sense. He's just leaving out the part that he is talking about line spacing, which is a function of metal half pitch.

Since Intel has the tightest metal half pitch, they also have the tightest line spacing. He's leaving out 2/3rd of the story in order to make you think 18nm line spacing is bad, when it is actually BIC.

 

[Khato]

Actually it's true in a sense. He's just leaving out the part that he is talking about line spacing, which is a function of metal half pitch.

Since Intel has the tightest metal half pitch, they also have the tightest line spacing. He's leaving out 2/3rd of the story in order to make you think 18nm line spacing is bad, when it is actually BIC.

Though is Intel using 18nm line spacing? I just am finding it quite bizarre that Abwx is stating that the tools have a precision of 18nm at best - they can get down below even that with ArF using more than double patterning if necessary. Hence why I'm inquiring as to where he came up with that specific 18nm figure.

 

[Phynaz]

This document from Toshiba shows Xeon simulation with 18mn minimum line spacing.

http://www.aspdac.com/aspdac2013/archive/pdf/3C-4.pdf

Of course that doesn't mean it's actually what Intel is using, but the math works out (32nm half pitch).

Also, this is logic, not DRAM, which is much denser.

 

[erunion]

But your chart actually does bring up a very interesting point - did TSMC simply change their line on the chart to correspond to the node label scaling rather than actual data? Because the similarities certainly make it appear as though such may be the case.

I had that thought as well. TSMCs graph does seem to be based on the node name. It seems TSMC only begrudgingly showed Intel 14nm as higher density because the node label as smaller. What other reason could they have to graph both 10nm nodes as equal?

Intel's entire point with their graph was to show that TSMCs lack of density scaling with 16nm is going to effect all future nodes. Yet TSMC showed their 10nm equal with Intel 10nm which would require TSMC 10nm to offer twice the scaling of a typical node.

 

[Ajay]

But according to common logic? TSMC replace their planar 20nm transistors with FinFETs and call it 16nm. Then they do a shrink and call it 10nm. They're just exploiting the mess node naming has become: it doesn't give any useful information anymore

^^ This is my final take away. When we have high volume production silicon in the hands of the folks who analyze this stuff (publicly) - then we'll have our answer. This war of words is pointless marketing babel from a technical standpoint.

/thread

 

[Homeles]

Hey, if TSMC does end up having better density than they've told us in the past, and that they actually do have density on par with Intel's 10nm, that's great. So many products rely on TSMC as a foundry, and the greater the progress, the better.

 

[Abwx]

Actually it's true in a sense. He's just leaving out the part that he is talking about line spacing, which is a function of metal half pitch.

Since Intel has the tightest metal half pitch, they also have the tightest line spacing. He's leaving out 2/3rd of the story in order to make you think 18nm line spacing is bad, when it is actually BIC.

I pointed that sub 18nm nodes are not possible neither for Intel
nor for TSMC given the state of the technology but anyway
can you point where i said that it is bad.?..If you cant , and you
cant indeed, it means that you are deliberatly trolling , worse ,
doing deffamation.

For a constructive discussion use my sayings as they are written
without trying to redefine them accordingly to your own mantra.

Though is Intel using 18nm line spacing? I just am finding it quite bizarre that Abwx is stating that the tools have a precision of 18nm at best - they can get down below even that with ArF using more than double patterning if necessary. Hence why I'm inquiring as to where he came up with that specific 18nm figure.

18nm is the max precision of ASMLs most advanced available tools
and that is with double or even triple patterning.

ASML’s TWINSCAN NXE platform is the industry’s first production platform for extreme ultraviolet lithography (EUVL). The NXE:3300B is the successor to the NXE:3100, offering 22 nm resolution with conventional illumination and 18 nm with off-axis illumination as well as improved overlay and higher productivity.

http://www.asml.com/asml/show.do?lang=EN&ctx=46772&dfp_product_id=842

 

[know of fence]

I disagree. Nothing in Intel's slide is misleading from what I can tell. Intel was comparing the actual transistor density between the two companies at the nodes specified. This is a perfectly valid comparison. TSMC's chart is the one that is somewhat misleading because they are convoluting the results with other metrics (i.e. improved layout) which does not actually represent what the Intel was showing. I don't blame TSMC because the chart does show them in a poor light but the comparison of actual transistor density is properly displayed in Intel's slide.

1. Five of the eight points are marked as "Forecast", even choosing words like "actual" or "data" is inappropriate for something like this. Not to mention we don't see a scale, not even a description for the Y axis, other than log scale. There is the old conundrum of whether logarithms should have units or not. I seem to remember I was taught to normalize units (off) before applying the logarithm function, so we can't have units as description, I guess. Well I had to infer that the Y-Axis denotes "area" from the slide title. But which area still remains vague, is it area to place a certain IC or is it just trivial Y = X² area of a square, that shrinks as you shorten the sides. I lean toward the latter.

2. What does the chart set out to show for the immediate future, with it's completely convoluted way to present data, It shows that 14nm is more dense than 16nm. Wow, guess what node also would be more dense than 16nm?
A. 15nm
B. 14nm
D. 13nm
E. 12nm
F. All of the above

3.Typically every node shrink is chosen such, that it basically halves the area. Twice as many transistors for the same area hence Moore's law and all that. This would read as 50% ahead in the chart presumably(?).
Intel's chart shows TSMC's [20] and [16] nodes at about the same hight. Why would TSMC go from 20 to 16ff if there is no area / no cheaper production to recoup the investments to be gained?

Also according to this graph the upcoming 14 nm process will only be 35% ahead of TSMCs 20 nm. Which should be good news for TSMC, since they both should arrive at the same time.

 

[Homeles]

2. What does the chart set out to show for the immediate future, with it's completely convoluted way to present data, It shows that 14nm is more dense than 16nm. Wow, guess what node also would be more dense than 16nm?
A. 15nm
B. 14nm
D. 13nm
E. 12nm
F. All of the above

I think you know this, but node labels are just that -- labels. A 14nm process isn't necessarily denser than a 16nm one, because those numbers have nothing to do with minimum feature size anymore.

Interestingly enough, Intel's 14nm process was originally labeled as 16nm.

Why would TSMC go from 20 to 16ff if there is no area / no cheaper production to recoup the investments to be gained?

There should be some, but they'll be minor given that they share the same BEOL. Regardless, it doesn't truly matter for TSMC if 16nm is denser or not -- they sell the wafers, not the ICs, so density is just a carrot to dangle in front of their customers. The point of 16nm (and I'm sorry to say, but it's quite obvious) is the improved performance gained from FinFETs, particularly at lower voltage.

 

[Phynaz]

I pointed that sub 18nm nodes are not possible neither for Intel
nor for TSMC given the state of the technology

Line spacing != feature size.