Interesting dispute brewing between Intel/TSMC

GreenChile

Member
Sep 4, 2007
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TSMC’s FinFET Density Claim Seems Questionable
Apparently TSMC is offering a unique perspective on node shrinks to dispute Intel's claim that they will be 35% ahead of TSMC in density at the 14/16nm node.
In essence, TSMC is claiming that, because the chip designers can trade off performance for density with a density-focused layout, this allows them to claim a "15% density advantage" over its 20-nanometer process, even with the same metal stack. Unfortunately, this doesn't pass the smell test because Intel, with its own designs, could do the exact same thing and have a denser metal stack, thereby nullifying any density "advantage" that TSMC can garner from an improved layout methodology. This -- not Intel's claims -- is what appears to be misleading here.
Nevertheless Intel will likely have 14nm long before TSMC has 20nm finfets (i.e. 16nm). This is surely the first of many battles to come between the two companies now that Intel is starting to invade their turf in the foundry business.
 

erunion

Senior member
Jan 20, 2013
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I saw this as well. Despite the headlines, it was mostly a non-denial. Talking about 20nm vs 22nm is irrelevant, Intel didn't claim 22nm was denser than 20nm.
 

jdubs03

Senior member
Oct 1, 2013
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I think the most interesting thing about TSMC's conference call and hence this article was that TSMC really seems confident about offering an extra 15% advantage over the original 16nm design. So 16nm+. From what I saw in their slides the performance advantage of shrinking to each node is 15% for 28nm to 20nm, and 20nm to 16FF. Adding another 15% at the same node adds some intrigue when 20nm and 16nm actually ship with products (which I think is H2 2014, Q4 2015)
 
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Abwx

Lifer
Apr 2, 2011
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TSMC’s FinFET Density Claim Seems Questionable
Apparently TSMC is offering a unique perspective on node shrinks to dispute Intel's claim that they will be 35% ahead of TSMC in density at the 14/16nm node.

Nevertheless Intel will likely have 14nm long before TSMC has 20nm finfets (i.e. 16nm). This is surely the first of many battles to come between the two companies now that Intel is starting to invade their turf in the foundry business.

We can be sure that the article writer is totaly unbiaised
when it comes to Intel....

Ashraf Eassa owns shares of Intel. The Motley Fool recommends Intel. The Motley Fool owns shares of Intel.
 

Bubbleawsome

Diamond Member
Apr 14, 2013
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Abwx

Lifer
Apr 2, 2011
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That same author has written many critical pieces about Intel, too ;-)

For example...

http://seekingalpha.com/article/1935731-intels-merrifield-looks-dead-on-arrival



And, look, he's even positive on TSMC!

http://seekingalpha.com/article/1722462-taiwan-semiconductor-looks-undervalued-ahead-of-key-drivers

Gee, guess it's possible to be objective *and* own stocks! What a concept! :)

Generaly i dont give credit to whoever speak of himself
at the third person....:biggrin:
 

Ajay

Lifer
Jan 8, 2001
15,332
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I think the most interesting thing about TSMC's conference call and hence this article was that TSMC really seems confident about offering an extra 15% advantage over the original 16nm design. So 16nm+. From what I saw in their slides the performance advantage of shrinking to each node is 15% for 28nm to 20nm, and 20nm to 16FF. Adding another 15% at the same node adds some intrigue than just when does 20nm and 16nm actually ship with products (which I think is H2 2014, Q4 2015)

The only way they get another 15% increase in density is if the metal layers have been shrunk as well. Otherwise, it does seem very dubious indeed. I know David Kanter (admittedly, not a process guy) said they he expects less from 20nm and 16FF than from traditional shrinks. This is because TSMC isn't scaling the metal layers down as much as they used to. If they've found a way to do better - well, kudos to them. Otherwise, it's probably marketing bologna.
 

Abwx

Lifer
Apr 2, 2011
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TSMC responded to Intel’s 14nm density advantage claim in the most recent conference call. It is something I have been following closely and have written about extensively both publicly and privately. Please remember that the fabless semiconductor ecosystem is all about crowd sourcing and it is very hard to fool a crowd of semiconductor professionals, absolutely. To see Intel's infamous density presentation click HERE.

9835d1390352099-tsmc-intel-density-comparison.jpg


Morris Chang – Chairman: So I now would ask Mark Liu to speak to TSMC's competitiveness versus Intel and Samsung:

Let me comment on Intel's recent graph shown in their investor meetings, showing on the screen. I -- we usually do not comment on other companies' technology, but this -- because this has been talking about TSMC technology and, as Chairman said, has been misleading, to me, it's erroneous based on outdated data. So I'd like to make the following rebuttal:

On this new graph, the vertical axis is the chip area on a large scale. Basically, this is compared to chip area reduction. On the horizontal axis, it shows the 4 different technologies: 32, 28; 22, 20; 14, 16-FinFET; and 10-nanometer. 32 is Intel technology, and 28 is TSMC technology so is the following 3 nodes, the smaller number, 20, around -- 14-FinFET is Intel, 16-FinFET is TSMC. On the view graph shown at Intel investor meeting, it is with the gray plot, showing here. The gray plot showed the 32- and the 20-nanometer TSMC is ahead of the area scaling and -- but -- however, with 16, the data -- gray data shows a little bit uptick. And following the same slope, go down to the 10-nanometer, was the correct data we show on the red line. That's our current TSMC data. The 16, we have in volume production on 20-nanometer. As C.C. just mentioned, this is the highest density technology in production today.


We take the approach of significantly using the FinFET transistor to improve the transistor performance on top of the similar back-end technology of our 20-nanometer. Therefore, we leverage the volume experience in the volume production this year to be able to immediately go down to the 16 volume production next year, within 1 year, and this transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger so that you don't need such a big area to deliver the same driving circuitry.

And for the 10-nanometer, we haven't announced it, but we did communicate with many of our customers that, that will be the aggressive scaling of technology we're doing. And so in the summary, our 10 FinFET technology will be qualified by the end of 2015. 10 FinFET transistor will be our third-generation FinFET transistor. This technology will come with industry's leading performance and density. So I want to leave this slot by 16-FinFET scaling is much better than Intel's set but still a little bit behind. However, the real competition is between our customers' product and Intel's product or Samsung's product.

Morris Chang – Chairman: Thank you, Mark. In summary, I want to say the following: First, in 2014, we expect double-digit revenue growth and we expect to maintain or slightly improve our structural profitability. As a result, we expect our profit growth to be close to our revenue growth. In 2014, the market segment that most strongly fuels our growth is the smartphone and tablet, mobile segment. The technologies that fuel our growth are the 20-SoC and the 28 high-K metal gate, in both of which we have strong market share. In 2015, our strong technology growth will be 16-FinFET. We believe our Grand Alliance will outcompete both Intel and Samsung, outcompete.

https://www.semiwiki.com/forum/content/3099-tsmc-responds-intel-s-14nm-density-claim.html
 
Mar 10, 2006
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Generaly i dont give credit to whoever speak of himself
at the third person....:biggrin:

I was simply pointing out the complete folly of your dismissal of somebody's analysis because they happen to invest based on what they believe to be true, particularly when said individual has pretty solid credibility of telling it like it is even when it goes against said individual's position.

Also, my identity is not a secret as I do participate in FS/FT rather frequently ;-)
 

AtenRa

Lifer
Feb 2, 2009
14,000
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This is because the driving of the transistor is much stronger so that you don't need such a big area to deliver the same driving circuitry.

Morris Chang is talking about the Transistor Size not what the designers will do. He is saying that because at 16nm they transition to FinFet transistors, the transistors themselves exhibit better electrical characteristics than 20nm planar at a smaller size.
So even without changing the metal stack, due to FinFets they have an extra reduction in transistor size of 15%.
 

NTMBK

Lifer
Nov 14, 2011
10,208
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Conspiracy!

Actually, truth be told, I was just really lacking for screen-name ideas when I made my account in 2006(?). I should have gone with something a bit more awesome :)

So that makes you 25 now then? ;)
 

witeken

Diamond Member
Dec 25, 2013
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Mar 10, 2006
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Morris Chang is talking about the Transistor Size not what the designers will do. He is saying that because at 16nm they transition to FinFet transistors, the transistors themselves exhibit better electrical characteristics than 20nm planar at a smaller size.
So even without changing the metal stack, due to FinFets they have an extra reduction in transistor size of 15%.

Oh, I see, so let's just ignore that Intel's 22nm gate pitch is already substantially smaller than TSMC's 28nm gate pitch. If you are talking transistor pitch and not metal pitch (which is what Intel's density graph was referring to), then Intel still "wins" the density argument.

Again, the foundries can't have it both ways. At any rate, this discussion is likely moot - you will be able to buy a 14nm Intel part at about the same time as a 20nm planar part from TSMC, and by the time 14/16FF are in customers' hands, Intel will be on the verge of the 10nm roll-out.

We'll just have to see how this all shakes out. There's more to the story than transistor performance/density as Intel's Bay Trail taught us (the design team really missed the mark in both optimizing for density as well as integration of key components), but Intel's SoCs have become much more competitive over time.
 
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AtenRa

Lifer
Feb 2, 2009
14,000
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Oh, I see, so let's just ignore that Intel's 22nm gate pitch is already substantially smaller than TSMC's 28nm gate pitch. If you are talking transistor pitch and not metal pitch (which is what Intel's density graph was referring to), then Intel still "wins" the density argument.

Where does Intel say that they only talking about metal pitch ??? The graph is about process density, that is the entire process, both Transistor and metal stack.
TSMC says that its 16nm FinFet will have another 15% density over its 20nm planar process. Because they are using the same metal stack as the 20nm process, that shrinkage comes solely from the FinFets.
 

AtenRa

Lifer
Feb 2, 2009
14,000
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Again, the foundries can't have it both ways. At any rate, this discussion is likely moot - you will be able to buy a 14nm Intel part at about the same time as a 20nm planar part from TSMC, and by the time 14/16FF are in customers' hands, Intel will be on the verge of the 10nm roll-out.

TSMC 20nm products will be released in H2 2014. Intel 14nm products will be released in H2 2014.
TSMC 16nm products will be released within 2015. Intel's 10nm products will not be released until the end of 2016 the earliest. And as things are going they may be delayed in to early 2017.

We'll just have to see how this all shakes out. There's more to the story than transistor performance/density as Intel's Bay Trail taught us (the design team really missed the mark in both optimizing for density as well as integration of key components), but Intel's SoCs have become much more competitive over time.

Baytrail T(tablet) is using the Ultra Low Power 22nm Intel process. But that process have the worst density against the other 22nm Intel processes.

Intel_22nm_table.png
 

GreenChile

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Sep 4, 2007
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Where does Intel say that they only talking about metal pitch ??? The graph is about process density, that is the entire process, both Transistor and metal stack.
TSMC says that its 16nm FinFet will have another 15% density over its 20nm planar process. Because they are using the same metal stack as the 20nm process, that shrinkage comes solely from the FinFets.
It doesn't matter as long as TSMC plans to keep the 20nm metal pitch for the 16nm node then there will be no density scaling from the shrink. The area taken up by each transistor remains the same between 20nm and 16nm. This is precisely what TSMC have stated they are planning to do.

The graph is referring to the density scaling which includes both gate pitch and metal pitch. The only scaling that will take place on TSMCs 16nm node is from better utilization of the more robust finfet transistors. Meaning they can reduce the size of the chip by around 15% by having fewer transistors. The article is pointing out that Intel can use those same techniques too so he feels it's a weak argument for TSMC to claim they will get 15% scaling.

Personally I think TSMC has a valid argument if true because the end result will still be a smaller chip even if the density remains the same but both sides seem to be correct depending on your point of view.
 

GreenChile

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Sep 4, 2007
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TSMC 20nm products will be released in H2 2014.
Baytrail T(tablet) is using the Ultra Low Power 22nm Intel process. But that process have the worst density against the other 22nm Intel processes.

Intel_22nm_table.png
Actually gate pitch is not the limiter for scaling. The tightest metal pitch is the limiting factor and the ULP process actually has a tighter metal pitch because thick metal lines are not needed due to low power.
 

Khato

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Jul 15, 2001
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Regardless of the exact cause for such, TSMC has been stating that they expect to see a 1.1x improvement in gate density for their '16nm' process over their 20nm process for over half a year now. The 15% figure matches up with their best case of SRAM, which apparently scales from 0.081um^2 to 0.07um^2. It is amusing how much they moved their 'dot' for that node on the chart though - they closed over twice the distance to Intel's 14nm despite the fact that a logarithmic scale should have them moving less than the linear difference. But ya know, they figure that investors don't know what they're looking at when it comes to a logarithmic scale, right? (The really amusing part is, well, who's to say that Intel didn't factor in TSMC's projected 1.1x density scaling going from 20nm to '16nm' when arriving at their 35% figure? Just because they made it a straight line to emphasize the lack of traditional scaling doesn't mean that their calculations didn't use TSMC's publicly released information that indicated a small amount of scaling.)

I especially enjoy the 10nm mark as there it's a matter of both companies making up numbers for the competition. At least Intel had TSMC's public statements/information to go on for the '16nm'/14nm node. But that's all the more reason why TSMC claiming that they're going to match Intel at that point is little more than posturing.

Regardless it's going to be quite interesting indeed to see where everything actually falls. Especially since Intel has yet to give us any technical details regarding their forthcoming 14nm process.
 

witeken

Diamond Member
Dec 25, 2013
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TSMC 20nm products will be released in H2 2014. Intel 14nm products will be released in H2 2014.
TSMC 16nm products will be released within 2015. Intel's 10nm products will not be released until the end of 2016 the earliest. And as things are going they may be delayed in to early 2017.
10nm will probably go into high volume production in Q4 2015.
 

know of fence

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May 28, 2009
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It is amusing how much they moved their 'dot' for that node on the chart though - they closed over twice the distance to Intel's 14nm despite the fact that a logarithmic scale should have them moving less than the linear difference. But ya know, they figure that investors don't know what they're looking at when it comes to a logarithmic scale, right?

Apparently nobody understands logarithmic scales, it's just like quantum mechanics. You don't know, but you can select it from a drop down menu. Though I heard that babys have a logarithmic intuition towards numbers, which quickly gets overruled by teaching them to count.

A logarithmic scale requires to know the actual numbers, because the scales are tricky, in their quality of being non linear. The following picture shows how the same difference of 1 can be a lot or very little.

275px-Comparison_of_the_sequence_1_to_10_and_their_logs_to_the_base_10.png
(Source: Wikipedia)

My knowledge of this is shaky at best, but I think that they use a logarithmic scale in order to produce a linear graph for relationships that actually are exponential. Basically it's a trick to straighten out a curve, to be able to easily interpolate a straight trend line into actual numbers, or in this case to show a breaking out of a trend.
 
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