Do you have any info whether tulsa can outperform AMD in MP space? I'm not sure for this part except that for IBM due to their superior X3 chipset. I guess this is one reason why Dell pick AMD opteron due to lack of scalability on Intel's chipset for MP. I heard IBM X3/Paxville had outperform AMD Opteron in one of benchmarks (cant remember the link).
Intel's Tulsa
- Thread starter ahock
- Start date
No, Tulsa cannot compete in the MP space, it is jsut trying to stop to slow down the bleeding somewhat, it is not a solution to the problem (and is not meant to be one).
Brown is correct...as to the X3 (Hurricane), the reason it outperformed in TPC is that it had a MUCH more expensive I/O (Fiber Channel and drives). The cost of the I/O was much more expensive than the rest of the system ($600-700k IIRC), and greatly effects the transaction based TPC benchmark...
I know you do mate, but (with respect) none of the IT people or engineers I've asked agree with you...they all agree that because TPC is purely transaction based, the I/O makes a HUGE difference (and many have suggested that it's the reason that IBM has never submitted a TPC system without the fiber...).
I know you do mate, but (with respect) none of the IT people or engineers I've asked agree with you...they all agree that because TPC is purely transaction based, the I/O makes a HUGE difference (and many have suggested that it's the reason that IBM has never submitted a TPC system without the fiber...).
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If I/O is the dominant factor, why does Unisys's 16S/32P Xeon MP system score 749,839 tpmC vs only 492,307 for IBM's 16S/32P Xeon MP system when both use FC storage systems?
http://tpc.org/results/individual_resul...isys/Unisys_es7000-one_16x-749K_es.pdf
http://tpc.org/results/individual_results/IBM/ibm.x460.tpc-c.5.6.es.032106.pdf
An interesting question...same processors, both use FC. It might be the extra 384MB of shared L3 cache on the Unisys system, which would explain why both AMD and Intel are planning on releasing server CPUs with large L3 on-board.
It also brings the price/performance level down dramatically ($3.33/tpmc vs $6.12/tpmc for the IBM)...of course that's still more than 50% higher than the HP DL585 with Opteron ($2.02/tpmc).
However, it still doesn't illustrate anything to do with FC...for that we would need to see 2 systems that were ~same, one with FC and the other without...
Imagine how people in Conroe, Tx feel. A lot of pub for them lately.
As for Tulsa, I know it isn't the "solution" to overtake what AMD is offering in MP space, but will Woodcrest be? Will they put that part on MP space (with dual FSB)? Intel's real answer in the MP x86 space probably won't be until a Nehalem based part with IMC and CSI Interconnects.
From the looks of things for the MP space thier first product on Core Architecture will be Clovertown MP/Tigerton which is a Dual Die Quad Core. Don't know of anything earlier actually.
Except that Cloverton will still have only 2 connections to the Northbridge (one for each socket). As there's no direct connection between the cores on-die (meaning that the MCM will need to use the NB for cache coherency), it will be handicapped...
Severly, especially with the use of a true FSB versus a hypertransport bus of some kind. That is going to need a shitton of coherent connections if the NB is going to be responsible for cache coherency as well as RAM and I/O. Will the new s771 for Xeon be enough?
Tigerton is a true quad core/single die processor is it not? If so, since all cache coherency and intercore communications can be on-die; won't it need fewer NB traces than it's predicessor?
Then, logically, could we see Intel handicap cloverton even more by forcing the communication to an inferior number of communication lanes just so they can remain on the same socket?
No, Tigerton and Cloverton are both MCMs (Multi-Core Modules)...
Cloverton is DP and Tigerton is MP.
It should be noted that Tigerton does have a "dedicated highspeed interconnect" instead of using the FSB.
http://news.com.com/Intel+pushes+back+I...s+Xeon/2100-1006_3-5911316.html?tag=nl
Edit: This is pointed out later in the forum, by Viditor, that the interconnect has been pushed back.
I believe that they are talking about CSI in that article (it's from last Fall...). CSI is now not due until the end of 2008 at the earliest.
Technically the first CSI product that is due out will be the Itanium based "Tukwila" part. It has IMC and CSI links. It plans to be out around early-mid 2008, unless there are setbacks (always a possiblity with Itanium stuff).
Viditor is correct in that we won't see CSI on an x86 part until end of 2008 at the earliest.
Also FYI, Tulsa's dual core implementation is not MCM (MCM like Smithfield and Pressler), but much more like how Conroe's dual core setup is.
100% correct here. Tulsa is going to have a shared L3 cache that is 16MB in size (simply massive). This allows for a lower number of cache coherency snoops between the cores that would otherwise be on the FSB. But they were talking about Togerton and Cloverton in the above, not Tulsa. Not sure if you were just pointing out a fact or misread it.
I am not dicussing anything on how good it will be just that it is their first solution with Core Architecture in the 4+ space.
Final performance will have to be seen when this solution is available.
Intel doesn't look to be moving to the single die implementation of Quad Core till they have the 45nm process, from the looks of things. Intel is using the Dual Die implementation of Quad Core, because it is the quicker solution to get the product out the door, or it could be just flexibility as you can address the Dual Core and Quad Core needs at the same time, with Clovertown being basically 2 Woodcrests.
Finally performance of this solution will have to be seen.
It is also alot cheaper in the case that one of the dual-cores is bad. They don't need to throw away the whole chip, just the half that would otherwise be bad.
I wasn't trying to guesstimate on performance as that depends on a lot more than just the interconnects. I'm aminly wondering if the new xeon s771 will be a high enough pin count to account for all the work that will have to be done back and forth to the NB. I'm no where near an expert in this area but, it seems to follow logic that with s771 xeon's being adequate for dual core and desktop dual cores on s775 either intel has done it's job in future proofing quite well in designing the sockets to scale do quad core or, we're going to be faced with yet another socket change when quadcore comes around. If yet another socket change becomes necessary, it's going to be hard to justify changing ALL of a companies servers out for quadcore instead of just having to do a processor swap.
yeah, how do you think cache coherancy is maintained between the two different CPUs in the server tested? The bigger problem is that there will be a 1066 FSB for 4 cores isntead of the current 1333 for 2 cores.
Please oh CPU designer, enlighten us great unwashed on how that is a problem.
You know the same about how a four socket Woodcrest system will perform as Viditor. Absolutly nothing.
well, we were talking about Clovertown which is a 4 core CPU and will have a 1066 FSB, meaning that it will have 266MHZ per core, and that is for memmory and cache cohernecy data. IF you don't think people around here know enough about CPUs to understand how things like low memmory bandwidth will affect performance you are mistaken. Personally, I am an electrical engineering student who has taken computer architecture classes, but more importantly, I can look at benchamarks of CPUs runnign at different FSB speeds and see that a lower FSB is bad. Now Woodcrest isn't too bottlenecked with each core getting 667MHZ of bandwidth, but with each core getting 266 MHz clearly you don't have to have a PHD to see that you are gonna have a big problem. ITs not like I'm the only one saying it, look at any site where people ahve a clue what they are talking about and you will see the same.
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