Yes, I know what IPC means, thank you. The better term is instruction per cycle; or instruction per clock cycle, but I digress. Let me put it this way:
A chip architect must consider 3 important things; ipc, frequency, and power budget. But since the design must be married to a process, he has to take the characteristics of the process into account in his design as well. A low power process may be more suitable to an ipc-heavy design, at the expense of clocks. A high performance process would favor higher frequencies, at the expense of ipc. So what prevents an ipc-heavy design from being ported to a high performance process? Nothing. But power budget may need to be increased. No free lunch here. So, to compare clocks of different chips at a given frequency is to ignore the design decisions necessitated by all four factors at the time of design. This is why I said, it may sound counterintuitive, but clock for clock comparisons are quite disingenuous because they totally ignore the strengths/weaknesses of each design. IMHO, therefore, IPC tests done in the vacuum of "clock for clock" comparisons need not be taken too seriously.