coercitiv
Diamond Member
Not really, I already said about HSW power saving features. When software reads the core frequency the core needs to be active in order to do so. IOW when CPU-z is reading the frequency then bclk should not be in a power saving state. So the question remains. Why is it showing 24MHz?
A screenshot of SKL running 100MHz bclk would suffice to answer the question. 😉
Uhm... one of the earlier leaks?