Intel?s 32nm Clarkdale Processor Review Emerges

[MODEL3]

http://en.expreview.com/2009/0...emerges.html#more-4484

Anyway, even if this review is not credible, You can tell from the Nehalem architecture,
that the 4MB (2 cores) L3 is around half of the ammount it needs, in order for the architecture to shine a little bit more.
(the 4MB version has the same hit in relation with a possible 8MB version that Core 7000 series have in relation with Core 8000 series (around 10%) (That is the good
scenario)

Does anyone know if and when we are going to see a 16MB (4 core) Nehalem based CPU?

Also, is Hkepc reliable?

http://global.hkepc.com/3673

 

[Denithor]

Why would you think this chip needs more cache to shine? It's exactly the same ratio as used in the full-blown i7 series - 2MB per physical core.

I don't know if these guys are legit or not. Personally I wouldn't make any decisions based on a leaked benchmark like this performed with who knows what hardware (engineering sample chip, unoptimized BIOS, etc, etc...). I'll just wait and see performance from known sites on release candidate silicon. Until then it's just a guess anyway - right up until launch Intel can make changes that will impact performance.

 

[MODEL3]

Originally posted by: Denithor
Why would you think this chip needs more cache to shine? It's exactly the same ratio as used in the full-blown i7 series - 2MB per physical core.

That's exactly what I imply.

I imply that the i7 is limited by the ammount of L3 cache that incorporates.(around -10%)

Although a Core i7 has QPI, with 533MHz DDR3 it still takes a hit with only 8MB of cache.

I am not sure, but I think that even with 667MHz DDR3, it will have this problem.

So if you add the possibility, that the "32nm Nehalem versions" will have perf. advances in relation with "45nm Nehalem versions" per MHz

(Like "45nm Core 2 versions", had perf. advances in relation with "65nm Core 2 versions" per MHz, (around 5%, not counting SSE4.1))

You can deduct, that it is possible for the "32nm Nehalem versions", to be even more L3 cache starved than "45nm Nehalem versions" (if L3 stays at 8MB (4 cores))

(like "45nm Core 2 versions" needed 12MB L2 cache instead of 8MB L2 cache of the "65nm Core 2 versions" to achieve that performance level)

So if you take account the fact, that in "2-core 32nm Nehalem versions", each core can access up to 4MB of L3 cache, whereas in 4-core versions each core can access up to 8MB of L3 cache then you can understand that in some cases the hit will be in higher percentage for "2-core versions" in relation with "4-core versions"

 

[deputc26]

Looks like the rumored departure of QPI was just that. It was a rumor that never did make sense. The power consumption numbers that I would be most interested in seeing are those when each proc is undervolted to min. stable voltage at equal clockspeeds. Given that i3/i5 (the review says one CPU z says the other, I believe CPU-z is correct as I don't believe i3 has hyper threading) goes to 4.0ghz stock, I would expect Intel's 20% less power claim for their 32nm process to be slightly optimistic, though I hesitate to question a company that consistently understates performance.

Edit: Model3 your data above looks suspect, DDR3 533 and 667 are not used by anyone I am aware of, 1066 is about the slowest and Clarksdale has half the logical cores with which to crunch that data. I sense a flame war brewing... let's keep this thread on topic.

 

[drizek]

The AES benchmark is really nice. Does anyone know if this will work on all AES implementations?

The improvements in power consumption are pretty welcome, although the performance isn't as impressive as what I had expected. Of course, these benchmarks aren't exactly the most thorough, and I imagine we will see better numbers in other scenarios.

 

[MODEL3]

Originally posted by: deputc26
Edit: Model3 your data above looks suspect, DDR3 533 and 667 are not used by anyone I am aware of, 1066 is about the slowest and Clarksdale has half the logical cores with which to crunch that data. I sense a flame war brewing... let's keep this thread on topic.

Although some RAM makers labels them 1066/1600/2133MHz DDR3, I don't like marketing departments messing with the terms and adding words like effectively in the logic of things.

The progress of Double Data Rate (DDR) memory is:

DDR 100/133/166/200/266 MHz

DDR2 200/266/333/400/533 MHz

DDR3 400/533/667/800/1066 MHz

When you read something else, is marketing terms.
Physically, this is the speed!

 

[ilkhan]

While true, all you are doing is confusing people. The I/O bus clock is indeed the numbers you list, but DDR transfers on rising and falling of that clock, effectively doubling it. Regardless, the official JEDEC names use the effective clocks. Confusing people doesn't help anything.

 

[deputc26]

Originally posted by: MODEL3

Originally posted by: deputc26
Edit: Model3 your data above looks suspect, DDR3 533 and 667 are not used by anyone I am aware of, 1066 is about the slowest and Clarksdale has half the logical cores with which to crunch that data. I sense a flame war brewing... let's keep this thread on topic.

Although some RAM makers labels them 1066/1600/2133MHz DDR3, I don't like marketing departments messing with the terms and adding words like effectively in the logic of things.

The progress of Double Data Rate (DDR) memory is:

DDR 100/133/166/200/266 MHz

DDR2 200/266/333/400/533 MHz

DDR3 400/533/667/800/1066 MHz

When you read something else, is marketing terms.
Physically, this is the speed!

Ahh, I considered the possibility that you were talking about true frequency but decided it was unlikely as few people do. I was unaware that i7 was bottlenecked by ram (in most applications) as even running dual channel instead of triple channel to the i7 has little impact on performance. Though some apps like archiving do benefit substantially from faster ram.

 

[heyheybooboo]

I'm always interested in performance gains seen from various simd extensions in individual apps so when you say ....

(Like "45nm Core 2 versions", had perf. advances in relation with "65nm Core 2 versions" per MHz, (around 5%, not counting SSE4.1))

I'd love for yah to PM me any linkage yah might have right at hand.

As far as the L2/L3 cache thing I've always held the belief that with the Core arch 2Mb/core is 'just right' and that is the point where diminishing return on performance gain is seen with adding more. Going from 1Mb to 2Mb is "Yeah, Baby!" - going from 2Mb--->3Mb will get yah something but nowhere near the same order of magnitude. I think both Anand and Tom's has touched on this from time to time. It's quite obvious if you stack everything up in a spreadsheet and compare clock-to-clock from a bunch of benchies.

With Clarksdale it's speculation and I'm running low on that. I suspect Intel has studied the cache hierarchy to death from Core to the integrated memory controller of i3/i5 and determined this (2Mb/per core L3) is a good starting point for Clarksdale at the price they are targeting.

Future versions beyond 2Mb/per core L3 may be coming - at a higher price. It's all about the money and price point, right?

 

[ilkhan]

heyheybooboo- theres a 1.5MB/core (3MB) version coming.

 

[MODEL3]

Originally posted by: ilkhan
While true, all you are doing is confusing people

Funny, I always liked better the: "Know the truth, and the truth will set you free."
So I am not the one that confusing people, it's JETEC's marketing policy.

Originally posted by: ilkhan
The I/O bus clock is indeed the numbers you list, but DDR transfers on rising and falling of that clock, effectively doubling it. Regardless, the official JEDEC names use the effective clocks. Confusing people doesn't help anything.

Probably You don't have a technological background, so if you are reading staff from sources like wikipedia you confuse things:

DDR SDRAM (double-data-rate synchronous dynamic random access memory) is a class of memory integrated circuits used in computers. It achieves nearly twice the bandwidth of the preceding "single data rate" SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency.

You have to focus on the text in bold.

Although DDR transfers on rising and falling of that clock, it does not double effectively the I/O bus clock at all (like you suggesting) it only effectively doubles the ammount of Data, that transfered in a set time.

If I wanted to stress your logic (or JETEC's, although they do it for marketing reasons) then they should have marketed the memory modules (pairs), that target dual channels memory bus with double speed labeling in relation with single memory modules.

Just joking.

After all, they have to leave something for the Motherboards Makers!

 

[ilkhan]

pretty much. So, its doubling the effective amount of work done, but not effectively doubling the bus clock? They could say it transfers 128bits per clock (per channel) (64 bits twice per clock). Would that make you happy?
And yes, its marketing reasons. But as long as its consistent it won't confuse folks.

 

[MODEL3]

Originally posted by: heyheybooboo
I'm always interested in performance gains seen from various simd extensions in individual apps so when you say ....

(Like "45nm Core 2 versions", had perf. advances in relation with "65nm Core 2 versions" per MHz, (around 5%, not counting SSE4.1))

I'd love for yah to PM me any linkage yah might have right at hand.

From Anand's review:

On average, Wolfdale ends up being just under 5% faster clock-for-clock than Conroe. Definitely not an earth shattering improvement, but an improvement nonetheless. Focusing in on specific benchmarks, Wolfdale can look even more impressive. Without taking SSE4 performance into account as we don't know how widespread SSE4 applications will be upon its arrival, Wolfdale will simply make competing more difficult for AMD's Phenom, but not impossible

As for SSE4.1 sorry I don't have something, just use a search engine.

Originally posted by: heyheybooboo
As far as the L2/L3 cache thing I've always held the belief that with the Core arch 2Mb/core is 'just right' and that is the point where diminishing return on performance gain is seen with adding more. Going from 1Mb to 2Mb is "Yeah, Baby!" - going from 2Mb--->3Mb will get yah something but nowhere near the same order of magnitude. I think both Anand and Tom's has touched on this from time to time. It's quite obvious if you stack everything up in a spreadsheet and compare clock-to-clock from a bunch of benchies.

With Clarksdale it's speculation and I'm running low on that. I suspect Intel has studied the cache hierarchy to death from Core to the integrated memory controller of i3/i5 and determined this (2Mb/per core L3) is a good starting point for Clarksdale at the price they are targeting.

Future versions beyond 2Mb/per core L3 may be coming - at a higher price. It's all about the money and price point, right?

Yes it's "just right" from a performance/cost point of view (I mean cost for Intel to manufacture the CPUs) For example for Wolfdale series (2 cores) If we give 8000 series a value of 100% in performance level,

Then:

7000 series with 3MB is like 90% (4MB "32nm Nehalem architecture" is like 90%)
5000 series with 2MB is like 80% (3MB "32nm Nehalem architecture" is like 80%)
3000 series with 1MB is like 67% (2MB "32nm Nehalem architecture" is like 67%)

I am just throwing numbers in order to make more clear my point, I don't consider the percentages correct in all situations (it depends from the application)

 

[MODEL3]

Originally posted by: ilkhan
pretty much. So, its doubling the effective amount of work done, but not effectively doubling the bus clock? They could say it transfers 128bits per clock (per channel) (64 bits twice per clock). Would that make you happy?
And yes, its marketing reasons. But as long as its consistent it won't confuse folks.

Also I want to make a clarification:
I used the term 533MHz DDR3
JETEC does not standarize the above Mem module as 1066MHz DDR3
The Standard name is DDR3-1066 (without the word MHz) and they do it for consistency (with SDR) reasons but also for marketing reasons.

 

[Idontcare]

Originally posted by: MODEL3

Originally posted by: ilkhan
While true, all you are doing is confusing people

Funny, I always liked better the: "Know the truth, and the truth will set you free."
So I am not the one that confusing people, it's JETEC's marketing policy.

Originally posted by: ilkhan
The I/O bus clock is indeed the numbers you list, but DDR transfers on rising and falling of that clock, effectively doubling it. Regardless, the official JEDEC names use the effective clocks. Confusing people doesn't help anything.

Probably You don't have a technological background, so if you are reading staff from sources like wikipedia you confuse things:

DDR SDRAM (double-data-rate synchronous dynamic random access memory) is a class of memory integrated circuits used in computers. It achieves nearly twice the bandwidth of the preceding "single data rate" SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency.

You have to focus on the text in bold.

Although DDR transfers on rising and falling of that clock, it does not double effectively the I/O bus clock at all (like you suggesting) it only effectively doubles the ammount of Data, that transfered in a set time.

If I wanted to stress your logic (or JETEC's, although they do it for marketing reasons) then they should have marketed the memory modules (pairs), that target dual channels memory bus with double speed labeling in relation with single memory modules.

Just joking.

After all, they have to leave something for the Motherboards Makers!

Just FYI it's JEDEC (Joint Electron Device Engineering Council), not JETEC...something I figure a person willing to critique others over their apparent lack of a technological background ought to know....

 

[MODEL3]

Originally posted by: Idontcare
Just FYI it's JEDEC (Joint Electron Device Engineering Council), not JETEC...something I figure a person willing to critique others over their apparent lack of a technological background ought to know....

I was just teasing him, how is it possible for me to be the judge for something like this?

After all (like I was saying yesterday to Anand, in a question I made him in his article for Globalfoundries I don't have a technological backround at all)

And even if I was, it is not in my character. I just want to make jokes, you know, to have fan in the forums.

It is just that you don't know me enough yet, otherwise you will knew that I was just kidding.

I didn't mean it. Also everyone can make mistakes or express themshelves wrongly (nomatter how good or not you are, eventually we all do)

If I wanted to make a Joke for myself it would be that after all, ilkhan used the word effectively (although it would be better to write "effectively" in quotes) in his point of view so I was kind of wrong saying that:

Although DDR transfers on rising and falling of that clock, it does not double effectively the I/O bus clock at all (like you suggesting) it only effectively doubles the ammount of Data, that transfered in a set time.

Anyway I hope ilkhan didn't took it too seriously, it doesn't worth it (not only from me but from anyone)

Now about JEDEC, yes I know, I just wrote it wrong the first time and from then it was copy/paste.

 

[Nemesis 1]

I am just reading not partaking. He is not me!

 

[ilkhan]

It didn't sound joking to me, but that doesn't always translate well into text.
I could nitpick several spelling and grammar errors in your posts, but I won't.
Technically you are correct, reality is being right can be confusing. lets just drop it.

 

[MODEL3]

Originally posted by: ilkhan
It didn't sound joking to me, but that doesn't always translate well into text.
I could nitpick several spelling and grammar errors in your posts, but I won't.
Technically you are correct, reality is being right can be confusing. lets just drop it.

Sorry


You can check some of my replies in other posts in order to see that I like to joke (attempts to make humor, failed is the missing word?)

You should see what I wrote to marmasatt, that was just asking an advice for what game to buy for his 6 years old daughter. I meant of cource no disrespect, I was just joking.

Now about my spelling & grammar, you should see, what some of the older members said in their replies in other Topics.
(I am from Greece and although I know English well I think, I have not made a conversation with anyone, since I got the "Lower" (13 years old).

But I can correct easily most of my mistakes, I just don't think that wasting time for this is Fun.

As for my "Forum Experience" although I watched around the last 3 years some technology forums I just started (before one month) to participate in Forums

I became a member in Anandtech's forum the last week only , but I think that already my English level went up a little bit!

 

[ilkhan]

Originally posted by: MODEL3
Now about my spelling & grammar, you should see...(I am from Greece

Totally forgiven. Don't let me say anything about spelling/grammar again.

Don't learn English from a forum, the spelling/grammar from the average poster is worse than yours.

 

[aigomorla]

oh man...

intel is not gonna be happy with this one.... not at all...

 

[xxceler8]

Nemesis 1 aka Model3, do you really need to troll this forum under 2 logins now?

 

[MODEL3]

Originally posted by: xxceler8
Nemesis 1 aka Model3, do you really need to troll this forum under 2 logins now?

Are you joking?

I didn't even understood what Nemesis 1 meant with


"He is not me"


Since he is a member from 2006, does anyone from the old members know him?

 

[IntelUser2000]

Originally posted by: deputc26
Looks like the rumored departure of QPI was just that. It was a rumor that never did make sense. The power consumption numbers that I would be most interested in seeing are those when each proc is undervolted to min. stable voltage at equal clockspeeds. Given that i3/i5 (the review says one CPU z says the other, I believe CPU-z is correct as I don't believe i3 has hyper threading) goes to 4.0ghz stock, I would expect Intel's 20% less power claim for their 32nm process to be slightly optimistic, though I hesitate to question a company that consistently understates performance.

Remember, the 3.06GHz is an Engineering Sample. If you look at the Lynnfield 2.66GHz reviews, you'll notice they also have HT enabled.

You can't really compare CPU power consumption when the whole system is being measured. 20% reduction on the CPU part could be a mere 5% reduction on the system as a whole. Plus, you gotta remember 30% less power consumption by Intel is at same performance. Clarkdale is faster and lower power here.

 

[Idontcare]

Originally posted by: MODEL3

Originally posted by: xxceler8
Nemesis 1 aka Model3, do you really need to troll this forum under 2 logins now?

Are you joking?

I didn't even understood what Nemesis 1 meant with


"He is not me"


Since he is a member from 2006, does anyone from the old members know him?

Don't worry about it MODEL3, we understand where you are coming from now.

Nemesis is a good a guy, quirky though so he rubs some people the wrong way. Don't take too much offense by being compared to him or even confused with him.

...xxceler8 - I am going to assume you were attempting to be humorous with your otherwise flamebait post here...but you really need to use some of the funny emoticons (like and ) when you make those kinds of posts as the otherwise it can lead to the interpretation that you are making personal attacks and that will only result in invitation to the moderators to scrutinize your account.

Originally posted by: Denithor
I don't know if these guys are legit or not. Personally I wouldn't make any decisions based on a leaked benchmark like this performed with who knows what hardware (engineering sample chip, unoptimized BIOS, etc, etc...). I'll just wait and see performance from known sites on release candidate silicon. Until then it's just a guess anyway - right up until launch Intel can make changes that will impact performance.

Back on topic - both expreview and hkepc are legit review websites, I regularly check them out with my handy google translator. However Denithor's gem here is in hitting the nail on the head when it comes to the bigger question, which is "what good is it to have preview benchmarks on beta hardware that is still unoptimized and not ready for shipping?"...microcodes that will slow down performance in some area (to gain stability) have yet to be finished, steppings eliminating the necessity certain performance-impacting microcodes have yet to be taped out, etc.

For me personally I could care less what the actual performance numbers are of Clarkdale samples and test platforms at this stage in the game...what is important to me though is that we are at the stage in the game where enough hardware exists (as needed to get thru this stage of the integration debug and verification steps) that some folks are compelled to try and leak benches onto the web.

If we weren't to this point yet (here in early Aug) then I'd be concerned that we weren't going to be seeing these chips for sale at Newegg within the next 5-6 months. It's a milestone, leaked benches on crappy buggy hardware, means nothing more to me.