Discussion Intel Nova Lake in H2-2026: Discussion Threads

[Joe NYC]

With a single CCD, both AMD and Intel will provide the most popular products. This is certain.

What may be interesting is how things shake out in the high end. Currently AMD is eating up the high end and thus the best margins.

I wonder how much of that "high end" is occupied by X3D vs non-X3D though. A single CCD Zen 6 X3D might be scary fast .... and the customer base for this product is highly educated so the "more cores" marketing won't have any sway.

Maybe for one generation, the 2 chiplet CPUs lose out (from already quite low base) since single CCD will cover more of the realistic MT demand people may have.

You are correct in the biggest sense of the discussion. TSMC is exempt due to its investment commitments in the US. I wouldn't bet heavily on the idea that their foreign made chips continue to stay "in the good graces" forever.

It is kind of scary to see MLID giving purchase timing advice based on tariffs a subject he is not trying to even superficially trying to get himself familiar with (outside of random retardation one can hear on the ancient device called TV - and I am not even talking about the business channels, where there is some intelligence).

For now, pretty much all of the US based fab companies (with fabs also abroad) are exempt from tariff, both of the major Korean semi / memory companies, of course TSMC. Which covers maybe 95% of PC space.

The companies that may be screwed are some of the remaining European and Japanese foundries, that are not currently investing in the US. I said "may be" because those tariffs have not been announced, and in any case, they will have small impact on PC space.

 

[511]

Maybe for one generation, the 2 chiplet CPUs lose out (from already quite low base) since single CCD will cover more of the realistic MT demand people may have.



It is kind of scary to see MLID giving purchase timing advice based on tariffs a subject he is not trying to even superficially trying to get himself familiar with (outside of random retardation one can hear on the ancient device called TV - and I am not even talking about the business channels, where there is some intelligence).

For now, pretty much all of the US based fab companies (with fabs also abroad) are exempt from tariff, both of the major Korean semi / memory companies, of course TSMC. Which covers maybe 95% of PC space.

The companies that may be screwed are some of the remaining European and Japanese foundries, that are not currently investing in the US. I said "may be" because those tariffs have not been announced, and in any case, they will have small impact on PC space.

I hope they don't tariff the equipment makers cause that would be dumb.

 

[eek2121]

16c has been on the market for like 6 years and it's completely irrelevant to this day.

Amazon alone moves multiple thousands of units per month. Sure, they aren’t the best sellers, but the volume is not as insignificant as you say.

 

[Covfefe]

This is incorrect for Zen5. Zen5 have whole front-end statically partitioned, it has decoders, op-cache and so on duplicated for each thread. They use significant amount of silicon just for smt which ain't used fot 1t at all.

Zen5's micro-op cache is shared, per Chips and Cheese's testing.

If both SMT threads are active, micro-op cache hitrate tends to drop as the two threads compete for cache capacity.

 

[MS_AT]

Zen5's micro-op cache is shared, per Chips and Cheese's testing

uOP cache has capacity of 6k entries, if SMT is active each threads gets 3k entries. Geneally only decoders are statically partitioned (one decoder per thread even if you disable SMT in the BIOS). Eveything else is either competively shared or watermarked.

 

[naukkis]

uOP cache has capacity of 6k entries, if SMT is active each threads gets 3k entries. Geneally only decoders are statically partitioned (one decoder per thread even if you disable SMT in the BIOS). Eveything else is either competively shared or watermarked.

Statically partitioning means that resources are split even for threads instead of competitive splitting where other thread can have more resources than other by demand. Competitive sharing was great when transistor budget was tight but statically partitioning and giving exclusive resources per thread saves power and reduces critical path execution delay so statically partitioning and clustering is what they do now. And if Intel and Amd are truthful of their smt cost competitively sharing resources also cost lots of silicon space too - even against just doubling some structures like decoders.

 

[Covfefe]

Statically partitioning means that resources are split even for threads instead of competitive splitting where other thread can have more resources than other by demand. Competitive sharing was great when transistor budget was tight but statically partitioning and giving exclusive resources per thread saves power and reduces critical path execution delay so statically partitioning and clustering is what they do now. And if Intel and Amd are truthful of their smt cost competitively sharing resources also cost lots of silicon space too - even against just doubling some structures like decoders.

Ah, sounds like this is a terminology issue. In the docs that moinmoin shared, AMD uses "statically partitioned" to refer to a resource that can never be used 100% by a single thread.

AMD uses "competitively shared" to mean that a single thread can use 100% of a resource, but when SMT is active the two threads have to split it.

AMD calls the 50/50 split (when SMT is active) for the micro-op cache competitive sharing, not static partitioning.

 

[inquiss]

Amazon alone moves multiple thousands of units per month. Sure, they aren’t the best sellers, but the volume is not as insignificant as you say.

So, peanuts then? It's a couple to a few percent of the volume.

 

[Kepler_L2]

Ah, sounds like this is a terminology issue. In the docs that moinmoin shared, AMD uses "statically partitioned" to refer to a resource that can never be used 100% by a single thread.

AMD uses "competitively shared" to mean that a single thread can use 100% of a resource, but when SMT is active the two threads have to split it.

AMD calls the 50/50 split (when SMT is active) for the micro-op cache competitive sharing, not static partitioning.

No, static partitioning is 50/50 split when SMT is active, competitively shared means each thread can use up to 100% of a resource even when SMT is active.

 

[Fjodor2001]

16c has been on the market for like 6 years and it's completely irrelevant to this day.

Intel and AMD disagrees with you since they are releasing ~50T CPUs for the consumer DT market in 2026.

Cope with it and embrace the future.

 

[jpiniero]

Intel and AMD disagrees with you since they are releasing ~50T CPUs for the consumer DT market in 2026.

Cope with it and embrace the future.

It's because of Wall Street.

Once AI Hype dies for good they will cut back.

 

[Fjodor2001]

It's because of Wall Street.

Once AI Hype dies for good they will cut back.

Has nothing to do with AI. If that would be the case they would add beefy NPUs instead of more general purpose cores.

 

[jpiniero]

Has nothing to do with AI. If that would be the case they would add beefy NPUs instead of more general purpose cores.

Oh I mean you meant Tops.

Anyway, Intel's 52 core is going to be ignored because DIY doesn't play Cinebench... they play games.

 

[adroc_thurston]

Intel and AMD disagrees with you since they are releasing ~50T CPUs for the consumer DT market in 2026.

You do understand that top SKUs are maybe 2% of the overall lineup sales?
They exist for bragging rights.

 

[Fjodor2001]

Oh I mean you meant Tops.

You can mean whatever you want, but your AI comment does not make sense. If Intel and AMD would (primarily) focus on AI for consumer DT, they would add beefy NPUs instead of more general purpose cores.

Anyway, Intel's 52 core is going to be ignored because DIY doesn't play Cinebench... they play games.

If you only intend to do mid-range gaming, I agree you can stay on old peasant CPUs with 6-8C CPUs. You're better off spending your money on the GPU.

But for other consumer DT segments, both AMD and Intel concludes that more cores/threads is the way to go. Otherwise they would not introduce ~50T CPUs in 2026. Or are you suggesting you are better at analyzing the market than both those companies?

 

[Fjodor2001]

You do understand that top SKUs are maybe 2% of the overall lineup sales?
They exist for bragging rights.

Link to source?

Also, you do understand that the current top SKU is what will be mainstream in a couple of years? Do you remember when 4C CPUs were top SKU? And similarly for 6C, 8C, etc?

 

[adroc_thurston]

you do understand that the current top SKU is what will be mainstream in a couple of years

That sure as hell happened with 16c parts over the span of 6 years.

 

[Fjodor2001]

That sure as hell happened with 16c parts over the span of 6 years.

It's what has already happened with 8C CPUs. 16C+ soon to follow.

16/24C is still top SKU, so not yet mainstream. When we get 24/48C CPUs as top SKU, 16C will become mainstream.

 

[adroc_thurston]

It's what happened with 8C CPUs

A good octacore hand been around 450 to 500 bucks since 2018?

 

[ondma]

You can mean whatever you want, but your AI comment does not make sense. If Intel and AMD would (primarily) focus on AI for consumer DT, they would add beefy NPUs instead of more general purpose cores.

If you only intend to do mid-range gaming, I agree you can stay on old peasant CPUs with 6-8C CPUs. You're better off spending your money on the GPU.

But for other consumer DT segments, both AMD and Intel concludes that more cores/threads is the way to go. Otherwise they would not introduce ~50T CPUs in 2026. Or are you suggesting you are better at analyzing the market than both those companies?

Intel is screwed big time here in gaming, IMO. Their P/E core architecture is going to kill them. If AMD goes to 12 core CCD, they can have 12 big cores on one CCD with v-cache. The ideal response: more cores with v-cache, and no need to allocate the threads to the proper cores.

Intel OTOH, will be stuck with 8 P cores per chiplet, and will have to either accept 2 chiplets to get more P cores, or assign the gaming to E cores, (or a mixture of both). This seems a horrible solution for a company that is already getting trounced in gaming, partly because of too much latency in their tile structure. Maybe, if the new v-cache equivalent actually materializes, it can compensate for this, but TBH, it seems like a scheduling nightmare with loads of extra latency compared to AMD with 12 homogenous cores on one CCD.

 

[Fjodor2001]

A good octacore hand been around 450 to 500 bucks since 2018?

Sweet. Now we'll soon get 16C at nice mainstream price too, and ~50T CPUs at fair price as well. No more need for überexpensive HEDT/Server platform to get that.

 

[adroc_thurston]

Intel is screwed big time here in gaming, IMO. Their P/E core architecture is going to kill them. If AMD goes to 12 core CCD, they can have 12 big cores on one CCD with v-cache. The ideal response: more cores with v-cache, and no need to allocate the threads to the proper cores.

Intel OTOH, will be stuck with 8 P cores per chiplet, and will have to either accept 2 chiplets to get more P cores, or assign the gaming to E cores, (or a mixture of both). This seems a horrible solution for a company that is already getting trounced in gaming, partly because of too much latency in their tile structure. Maybe, if the new v-cache equivalent actually materializes, it can compensate for this, but TBH, it seems like a scheduling nightmare with loads of extra latency compared to AMD with 12 homogenous cores on one CCD.

Atoms are perfectly capable for video games.

 

[adroc_thurston]

Sweet. Now we'll soon get 16C at nice mainstream price too, and ~50T CPUs at fair price as well. No more need for überexpensive HEDT/Server platform to get that.

But you're not getting it at a nice mainstream price.

 

[Fjodor2001]

But you're not getting it at a nice mainstream price.

Oh, you've got access to the Intel/AMD price list for NVL-S and Zen6? Link to source? Oh, and by the way, you forgot to provide the link to the source for your previous 2% market share claim, so you can add that as well. Unless it was all just guessing/BS as usual.

Also, if you really think the 16C SKUs will not be provided at mainstream price, then what do you think the 52C CPUs will cost? Remember that 52C will be on the consumer DT platform, thus for consumers. So for it to make sense, it must be priced accordingly.

 

[adroc_thurston]

Oh, you've got access to the Intel/AMD price list for NVL-S and Zen6? Link to source? Oh, and by the way, you forgot to provide the link to the source for your previous 2% market share claim, so you can add that as well. Unless it was all just guessing/BS as usual.

man this kid really expect everyone to spoonfeed him.

then what do you think the 52C CPUs will cost?

money.