Discussion Intel Nova Lake in H2-2026: Discussion Threads

[lemans24]

Here is all what we know about Nova Lake in terms of Improvements

• IO tile is Intel 3
• SoC is 18A with 4LPE Arctic Wolf cores and IMC
• compute is N2(8+16)/18AP depending on SKU
• GPU is 18AP/Intel 3(not totally sure about this maybe based on XE3/XE3P)
• Xe3 Display Engines and Xe4 Media engine with professional codec support
• minimum 70 TOPS Die waste Unit
• Panther Cove with 4MB Shared L2 for P cores
• Arctic Wolf E Cores(likely 20% IPC Improvements over Darkmont according to Raichu).
• AVX 10(aka AVX -512 Support)
• bumped up core counts for Ultra 5 will beat Ultra 9 285K easily in both ST and MT by a decent margin
• big Last Level Cache SKU with 144MB L3 cache for a single 8+16 tiles

anything else i miss?

will there be an I/O tile at all ?? thought it would be integrated into Soc since it is 18A

 

[511]

will there be an I/O tile at all ?? thought it would be integrated into Soc since it is 18A

IO is still different they are retaining the design
IO+SoC(18A)+Compute+iGPU

 

[OneEng2]

Their margin pressure is due to TSMC as well plus their Fabs utilization dropping due to wafers at external.

That is certainly part of the margin issue. I believe that Intel has been subsidizing their low margin business with their high margin business for quite some time. Now, they are in a position where they are getting killed in many of their traditional high margin products.

In addition to this, Intel have embarked on a mission to compete head to head with TSMC for the cutting edge node crown........ wow. Good luck to them.

This is a prohibitively expensive venture to try to amortize across a fraction of the unit sales that TSMC has.

It's a near "perfect storm" for Intel.

 

[LightningZ71]

Cache is king: dual bLLC Nova lake rumors

https://videocardz.com/newz/amd-ryzen-dual-x3d-and-intel-nova-lake-dual-bllc-leaks-surface-almost-simultaneously

Video Cardz Article

 

[igor_kavinski]

Cache is king: dual bLLC Nova lake rumors

That's really weird. Now they are gonna play cache wars?

And AMD previously thought it was too expensive but now they are seeing inference related gains?

How much gains are we talking about here?

 

[Saylick]

That's really weird. Now they are gonna play cache wars?

Begun, the Cache Wars have:

 

[ToTTenTranz]

Cache is king: dual bLLC Nova lake rumors

https://videocardz.com/newz/amd-ryzen-dual-x3d-and-intel-nova-lake-dual-bllc-leaks-surface-almost-simultaneously

Video Cardz Article

Not sure why these websites are comparing Nova Lake to a dual-X3D Zen5.
Nova Lake is late 2026 whereas the dual-X3D should be coming out a year before. Big-LLC Nova Lake should be a Zen6 competitor.

 

[igor_kavinski]

Not sure why these websites are comparing Nova Lake to a dual-X3D Zen5.

They seem to be insinuating that the bLLC chip rumor is so strong that AMD wants to increase their X3DD marketshare before Nova Lake arrives because obviously consumer dollars are limited so if they already have a decent enough chip, they may not see much reason to ditch their existing Ryzen X3DD unless the NVL bLLC chip shatters every record out there.

Due to differing caching schemes, the NVL bLLC may hypothetically have certain advantages over X3DD (some workloads may really like the Intel approach).

 

[adroc_thurston]

some workloads may really like the Intel approach

?

 

[igor_kavinski]

?

Intel bLLC may not simply be a victim cache. What if it preloads data too?

 

[adroc_thurston]

may not simply be a victim cache.

Yeah it is, all modern L3s are NINE.

What if it preloads data too?

Do you understand how cache prefetchers work?

 

[igor_kavinski]

Do you understand how cache prefetchers work?

Not as much as you do. Your point?

 

[Tigerick]

Not as much as you do. Your point?

SMARTDRV.EXE

 

[511]

X3D.exe
A modern way to download 3D cache on your CPU

 

[Geddagod]

Cache is king: dual bLLC Nova lake rumors

https://videocardz.com/newz/amd-ryzen-dual-x3d-and-intel-nova-lake-dual-bllc-leaks-surface-almost-simultaneously

Video Cardz Article

Dual bLLC matters as little here as it does for AMD if they also adopt AMD's strategy of not having the L3 being shared by both CCDs, which I think they will.
Or maybe since Intel's L3 latency is already so bad they think that having a large, unified L3 with even worse latency wouldn't be too bad of an issue for the capacity increase lol.

 

[igor_kavinski]

Or maybe since Intel's L3 latency is already so bad they think that having a large, unified L3 with even worse latency wouldn't be too bad of an issue for the capacity increase lol.

Intel's eDRAM based i7-5775c was able to do pretty well against even Comet Lake CPUs considering its age. If Intel is doing bLLC, they must have the required test data showing its effectiveness, enabling them to justify all the silicon real estate it would take.

 

[igor_kavinski]

https://videocardz.com/newz/intel-confirms-avx10-2-512b-support-for-future-intel-core-series

The 52 core monster running AVX10.2/AVX-512 code is one use case where AMD may have trouble beating Intel due to having to compete with actual physical threads with their SMT virtual threads.

 

[adroc_thurston]

The 52 core monster running AVX10.2/AVX-512 code is one use case where AMD may have trouble beating Intel due to having to compete with actual physical threads with their SMT virtual threads.

They don't because AMD SIMD implementation is world-class.

 

[igor_kavinski]

They don't because AMD SIMD implementation is world-class.

I don't doubt that but unless the Intel CPU is bandwidth constrained, I don't see how virtual threads could beat real threads.

 

[adroc_thurston]

I don't doubt that but unless the Intel CPU is bandwidth constrained, I don't see how virtual threads could beat real threads.

You gotta hide latency somehow you know.

 

[LightningZ71]

After seeing some of the recent leaks on the whole bLLC setup. I'm honestly less impressed. If true, the 8+16 CCDs just double their L3 from 3MB per core to 6. While that is certainly a lot, it's not as impressive as going from 4MB to 12MB for the X3D cache chips. It'll certainly help, especially in the cases where 36 MB spilled a lot and 72 MB doesn't spill at all, but it's not going to be as big as AMD'S is.

 

[511]

After seeing some of the recent leaks on the whole bLLC setup. I'm honestly less impressed. If true, the 8+16 CCDs just double their L3 from 3MB per core to 6. While that is certainly a lot, it's not as impressive as going from 4MB to 12MB for the X3D cache chips. It'll certainly help, especially in the cases where 36 MB spilled a lot and 72 MB doesn't spill at all, but it's not going to be as big as AMD'S is.

4.5 Mb per cluster for base and 13.5 for bLLC. All L3 is shared between cores and NVL has 2 Cores sharing L2 So the effectively is 4 E core cluster of size 4E and 4 P core cluser of size 2 P

 

[deasd]

Cache is king: dual bLLC Nova lake rumors

https://videocardz.com/newz/amd-ryzen-dual-x3d-and-intel-nova-lake-dual-bllc-leaks-surface-almost-simultaneously

Video Cardz Article

Those are just unreliable rumors on both side, Videocardz's attempt which reporting them together to make them look real is hilarious

https://twitter.com/x/status/1953453103522390193

https://twitter.com/x/status/1953098878083055852

 

[msj10]

After seeing some of the recent leaks on the whole bLLC setup. I'm honestly less impressed. If true, the 8+16 CCDs just double their L3 from 3MB per core to 6. While that is certainly a lot, it's not as impressive as going from 4MB to 12MB for the X3D cache chips. It'll certainly help, especially in the cases where 36 MB spilled a lot and 72 MB doesn't spill at all, but it's not going to be as big as AMD'S is.

it's 144MB per one 8+16 tile so 4x the regular config.