Discussion Intel Nova Lake in H2-2026: Discussion Threads

[LightningZ71]

You won't be fitting 48 e cores in the space of an 8+16 die. The e core quad complex is larger than a P cores. The likely best configuration would be a performance for with 2+P die(extra dark silicon for higher clocks), 8 regular P die, enlarged L3 on a die that uses HP libraries + a second die with 40 e cores in ten quads on a die that uses HD libraries. 50 cores, maximum ST, tons of MT.

Lower end parts can just use either DIE as needed, like the 12400 with only P cores, or edge devices with E cores only. Maybe a special throughput product with 80 e cores or a K special with 20 P cores.

 

[poke01]

I actually think Nova Lake will be bigger than alder lake and arrow lake. It’s one of those architectures where you will instantly notice the difference in a good way

 

[DavidC1]

You won't be fitting 48 e cores in the space of an 8+16 die. The e core quad complex is larger than a P cores. The likely best configuration would be a performance for with 2+P die(extra dark silicon for higher clocks), 8 regular P die, enlarged L3 on a die that uses HP libraries + a second die with 40 e cores in ten quads on a die that uses HD libraries. 50 cores, maximum ST, tons of MT.

Gracemont Quad was only about 15% larger than a P core, and Uncore portion takes up quite a bit. Skymont quad is still not enormously larger than a P core either.

Now that's changing again on Novalake gen. However, 32 cores should be easily doable.

But it won't fly with consumers, even HEDT. Even just 10% slower on ST makes it a deal breaker, and I assume with E cores having ~5% perf/clock advantage, the clock difference means the gap will be about 20%, a significant number.

Consumer gaming chips are the most demanding bunch to make. You need highest ST performance, very good MT performance, fairly low cost(meaning small die size) and do all that in a socketed system with widely varying memory and motherboard configurations, sometimes down to 6-7 generations of compatibility.

That would be far more optimum for those who really need to crunch numbers. (8P+16E) + (48 E) = 72 total cores (plus any LP-E cores). That would be far more powerful. But, yes, out of convenience and mass production, Intel will reuse the 8P+16E tile.

It's not just convenience. Having different core counts on different tiles means different communication, cache, and IO latency. If you are impacted by different tiles on current Ryzen chips with identical links to the IO die and identical compute modules, what will happen when one has 8P+16E in one tile and 48E in another?

On the Ryzen chips when it goes to another chip it means different cache latencies and gamers optimized based on that. On a different core module it means an entirely different uarch. With such different setups everything is affected, down to even storage performance.

When the first Athlon came out reviewers noted it had an advantage processing IO performance, thus storage performed better.

 

[LightningZ71]

All it takes for good 1t /ST performance is a pair of P cores. You can sacrifice a pair of quads to have a pair of P cores available to give you high ST performance while still having 32 e-cores. Case in point, Alder Lake and Raptor Lake U class laptop chips. They are all quite responsive on the i3 and above side because they have at least one or two P cores. If you really want to get ridiculous, you can combine two of those for 4p+64e and go torture cinememe all day long.

 

[OneEng2]

That has been Intel's plan all along. The image below was 5 years ago. More NPU for corporate employees, more graphics for gamers, more compute for creators, etc. Pick and choose based on need. It looks like Nova Lake is finally the start of that.

https://images.anandtech.com/doci/16021/Section%208%20%2821%29.jpg

Interesting. 2020 and it took until 2024 for tiles to be released at Intel in the consumer market.

It will be interesting to see how quickly Intel can execute on this strategy.... and how effectively. ARL seems to have run afoul of similar issues that AMD Zen 2 had. It will be interesting to see if NVL is Intel's Zen 3 moment.

AMD did it, but I dont know if lightning will strike twice.

AMD changed their fortune by giving up on the mantra "Real Men Have Fabs".... and then it took a hot moment for them to turn the ship around.

I actually think Nova Lake will be bigger than alder lake and arrow lake. It’s one of those architectures where you will instantly notice the difference in a good way

Doesn't seem like a great business idea to make an even bigger and more expensive CPU than ARL (and LNL). Intel needs to start making processors they make a profit on.

I have a bad feeling that Intel is currently in a similar situation to where AMD was with Bulldozer (although architecturally not so bad). I can see lots of lost market and some tough years ahead for Intel as they transition their business .... and their architecture to a more profitable model.

 

[DavidC1]

All it takes for good 1t /ST performance is a pair of P cores. You can sacrifice a pair of quads to have a pair of P cores available to give you high ST performance while still having 32 e-cores. Case in point, Alder Lake and Raptor Lake U class laptop chips. They are all quite responsive on the i3 and above side because they have at least one or two P cores. If you really want to get ridiculous, you can combine two of those for 4p+64e and go torture cinememe all day long.

You'll lose performance on most applications though. 8+16 is done because the 8 cores cover vast majority of the workloads. So even on Unified Core, if they adopt a similar strategy to Zen + Zen C, then there needs to be a Fast + Slow config. Plenty of complaints still exist.. Imagine if there was only 2x Fast cores.

Laptops are ok since you are losing some performance by moving to that form factor in the first place. The -U class laptops have performance equal to a Celeron in terms of ST, or oftentimes less in terms of responsiveness due to power management features.

Interesting. 2020 and it took until 2024 for tiles to be released at Intel in the consumer market.

They screwed up obviously. It mentions "Persistent Memory" meaning Optane DRAM plans for PC was real.

All these talks about tiles allowing quick configurations still hasn't materialized. So far all we got was Meteorlake and Arrowlake, and Arrowlake is sometimes faulted for having the last gen E core uarch for the LPE core.

And you have configurations changing generation to generation. LNL is different from ARL and PTL is again different, and NVL changes it again. The reality is I think such slide is more of a utopia, because you have to sacrifice something for such flexibility.

 

[Io Magnesso]

As expected, I understand that there are people who want to complain that there are only 2 cores of P cores. As expected, it's not as bad as Celeron even with -U SKU...
It's also about the grade...
At least I don't think all -u SKUs have a problem

 

[LightningZ71]

There are always down binned parts in their stack. I'm referring to what the achievable bin is, not the die recovery performance.

 

[OneEng2]

They screwed up obviously. It mentions "Persistent Memory" meaning Optane DRAM plans for PC was real.

All these talks about tiles allowing quick configurations still hasn't materialized. So far all we got was Meteorlake and Arrowlake, and Arrowlake is sometimes faulted for having the last gen E core uarch for the LPE core.

And you have configurations changing generation to generation. LNL is different from ARL and PTL is again different, and NVL changes it again. The reality is I think such slide is more of a utopia, because you have to sacrifice something for such flexibility.

I think the chiplets/tiles concept is very good for the bottom line as you can utilize the God Awful expensive node process for the compute tile only, and put everything else on a less expensive node. Additionally, you can keep the individual die sizes down to get yields up.

The down side is the latency. It seems like AMD has managed to get a handle on this since Zen 3. I believe that Intel will also get a handle on it.... in time.

From a profitability standpoint, I think tiles are an absolute must have for Intel. I am pulling for them to iron out their latency issues.

 

[igor_kavinski]

I have a bad feeling that Intel is currently in a similar situation to where AMD was with Bulldozer (although architecturally not so bad).

The situation is pretty bad. 285K isn't worth the high price (people can't eke out extra performance from it as well as they can from a 14900K), BIOS from most vendors are immature still and there are annoying problems where enthusiasts can't get things working as smoothly as 12/13/14th gen (DLVR cited as a real pain by most of them).

I myself suffered a whole afternoon with this incredible issue that just cries "half baked release": https://forums.anandtech.com/threads/arrow-lake-builders-thread.2622775/post-41475875

I have NEVER ever faced that issue with my Alder Lake and it was looking like I would spend days troubleshooting the issue so just plain gave up. If this were not a tinker machine and instead my only daily driver, I probably would've retired it to junk machine status and gotten something that actually works consistently and reliably, which right now is Ryzen.