Discussion Intel Nova Lake in H2-2026: Discussion Threads

[511]

Unified Cores will bring efficiency, but the problem is node gains are crashing. 14A is just 30% more density, meaning in terms of density it's equal to 1/3 of a node. Basically you need 6 years to get same density gains as 2 years.

Not to mention SRAM has stopped scaling also 20-30% density in is going to be the norm

If Arrowlake with 2 process node gains when the gains were big with new uarch in both cores got us what we got now, even if we assume uncore wasn't terrible. This is also why 60% for Novalake isn't that surprising. The bad part of Novalake isn't MT(which is really good), but ST.

What happens when density part crashes to 1/3 with future?

It has already crashed lol starting N3 FinFlex was a clever design trick to give more density/performance out of a given node.

 

[Io Magnesso]

Not to mention SRAM has stopped scaling also 20-30% density in is going to be the norm

It has already crashed lol starting N3 FinFlex was a clever design trick to give more density/performance out of a given node.

Indeed
There's a useful thing called FINFLEX
Although the TSMC process is indeed absolute at density I don't know if TSMC can actually achieve the transistor density published on the process node.

It's not impossible, but it's really expensive

In the past, the transistor density was lower than the nominal value of TSMC in N5.

 

[SmokSmog]

 

[Fjodor2001]

I am finding it hard to see how people will utilize 52 cores. I keep thinking that all that die space could do so much more and for more people if it were used a different way.

What would you use the die space for instead? Bigger NPU perhaps.

Going a bit further, how will you feed such a beast? I suppose you could move the desktop up to higher bandwidth memory than DDR8000 (perhaps RDIMMs at 16000MT?)... or move to a quad channel memory setup?

Yes, DDR8000+. Also, AMD is going for 48T with Zen6, so they are in similar situation but will not support as high memory speed IIRC. I guess both have concluded that memory bandwidth will not be an issue for most workloads.

Still, it's an awful big cost in die size, MB layout, and RAM

A lot of the cores are E cores, which are tiny. About 1/3 of a P core, IIRC. So die should not have to be that expensive. And I don’t see why MB or RAM should be expensive either.

That said, it’s the top SKU and partly on N2, so it won’t be cheap either of course. But still, it’s in the regular DT lineup, so likely it will be priced accordingly and not too high.

 

[dullard]

I am finding it hard to see how people will utilize 52 cores. I keep thinking that all that die space could do so much more and for more people if it were used a different way.

While 2028 is still a few years away, it is STILL hard to imagine that so many cores will be useful in consumer electronics.

Going a bit further, how will you feed such a beast? I suppose you could move the desktop up to higher bandwidth memory than DDR8000 (perhaps RDIMMs at 16000MT?)... or move to a quad channel memory setup?

Still, it's an awful big cost in die size, MB layout, and RAM to cater to cinebench isn't it?

You really make it sound like this will be going into a lot of consumer electronics. It won't.

For starters, 52 cores is not going into most consumer electronics. It'll be the Ultra 9 CPU which is looking awfully similar to bringing the Extreme Edition line back (in specs and probably in price). According to the rumors, Intel is bringing back the Ultra 3 line for the bulk of consumer electronics (4P + 8E + 4LP-E) or (4P + 4E + 4LP-E). Amongst Meteor Lake, Lunar Lake, and Arrow Lake there was just one Ultra 3 CPU available.

It looks increasingly like Intel will have three main options: (1) Two CPU tiles for computational heavy CPUs, (2) one CPU tile + one cache tile for cache heavy tasks like gaming, and (3) just one CPU tile and probably a space filler tile for the rest of users. The die space IS doing so much more when users get to pick and choose the die space and how it is utilized.

Quad channel memory is the simplest way to feed it. Motherboard tracing will be much more complex, but that is a problem that is already solved. Note: I have no information that Intel is doing quad channel, but that would be the simplest way to address your concern.

It isn't a big cost in die size because only the few people who buy them will pay for it. And even though we act like die space is expensive, in a CPU that probably will sell in the $1000 range, one more tile is actually a small fraction of that cost. The RAM itself isn't any more expensive either. Just a more complex motherboard.

Finally, if you think Cinebench is the only reason for high-throughput computations, then you should probably go learn a few things about various consumer uses before posting.

 

[poke01]

then you should probably go learn a few things about various consumer uses before posting.

He’ll be gone for a while then





/s

 

[511]

He’ll be gone for a while then





/s

Meme didn't load if you posted any if not you wasted space on my screen just like Intel wasted die space on NPU.

 

[OneEng2]

Finally, if you think Cinebench is the only reason for high-throughput computations, then you should probably go learn a few things about various consumer uses before posting.

Please provide a few examples.

 

[Io Magnesso]

You really make it sound like this will be going into a lot of consumer electronics. It won't.

For starters, 52 cores is not going into most consumer electronics. It'll be the Ultra 9 CPU which is looking awfully similar to bringing the Extreme Edition line back (in specs and probably in price). According to the rumors, Intel is bringing back the Ultra 3 line for the bulk of consumer electronics (4P + 8E + 4LP-E) or (4P + 4E + 4LP-E). Amongst Meteor Lake, Lunar Lake, and Arrow Lake there was just one Ultra 3 CPU available.

It looks increasingly like Intel will have three main options: (1) Two CPU tiles for computational heavy CPUs, (2) one CPU tile + one cache tile for cache heavy tasks like gaming, and (3) just one CPU tile and probably a space filler tile for the rest of users. The die space IS doing so much more when users get to pick and choose the die space and how it is utilized.

Quad channel memory is the simplest way to feed it. Motherboard tracing will be much more complex, but that is a problem that is already solved. Note: I have no information that Intel is doing quad channel, but that would be the simplest way to address your concern.

It isn't a big cost in die size because only the few people who buy them will pay for it. And even though we act like die space is expensive, in a CPU that probably will sell in the $1000 range, one more tile is actually a small fraction of that cost. The RAM itself isn't any more expensive either. Just a more complex motherboard.

Finally, if you think Cinebench is the only reason for high-throughput computations, then you should probably go learn a few things about various consumer uses before posting.

That's right, I'm not buying a multi-core CPU just for Cinebench
To be honest, I'm also interested
I have a solid use for it

 

[Io Magnesso]

Having options is a good thing
Basically, it is said that ordinary people do not need more than 8(16t) cores.
In that case, even a CPU with 8 cores or more will get the title of cinebench.

Any use exists

 

[gdansk]

Any use exists

And if we may reduce this to absurdity, why not put 288 cores in a 1851 pin socket?

 

[511]

And if we may reduce this to absurdity, why not put 288 cores in a 1851 pin socket?

we can definitely put 288 P4 Cores in 1851 and @igor_kavinski would buy it

 

[gdansk]

we can definitely put 288 P4 Cores in 1851 and @igor_kavinski would buy it

We should be able to fit at least 80 'monts in a dual tile setup. Give the throughput people maximum throughput, Intel.

 

[511]

We should be able to fit at least 64 to 80 'monts in a NVL-S size. Give the people their throughput, Intel.

the P core: E core ratio should be a little less on NVL but yeah 64 Arctic Wolf is definitely possible

 

[gdansk]

the P core: E core ratio should be a little less on NVL but yeah 64 Arctic Wolf is definitely possible

Of course, I don't fault them for building with what they have. It might make sense for them to try novel constructions.
But the part that more people want (max gaming performance in one die) should not be crucified upon a cross of throughput. If Intel does SKU shenanigans to make the dual tile part look appealing then it is a mistake.

 

[511]

Of course, I don't fault them for building with what they have. It might make sense for them to try novel constructions.
But the part that more people want (max gaming performance in one die) should not be sacrificed on a cross of throughput. If Intel does SKU shenanigans to make the dual tile part look appealing then it is a mistake.

Yeah but in the end it's up to Intel to get their priorities right they just need to have 15-20% better gaming performance than X5 X3D SKU for NVL bLLC.

 

[Io Magnesso]

And if we may reduce this to absurdity, why not put 288 cores in a 1851 pin socket?

It may be possible if the core per one is made incredibly small...

 

[dullard]

And if we may reduce this to absurdity, why not put 288 cores in a 1851 pin socket?

At 125 W base power, that leaves 0.43 W per core. Which Intel cores work optimally at that level? Heck if you go to 250 W for turbo that is still only 0.87 W per core. You end up in a situation where the cores become highly-inefficient and take even more power to get each unit of the work done. Power that they don't have.

Plus the cost. Yes, going from 26 to 52 cores is just one more tile with a manageable cost. But going to 288 cores with Nova Lake would be 10 additional tiles. Now price is a huge issue.

Plus the physical space. Putting that many cores together with our current nodes puts the cores far apart. Core to core latency would skyrocket.

288 cores might eventually be worthwhile. But we are far, far from that ideal. Especially for consumer parts. The node and software that can be effectively multi-threaded are far behind that.

 

[gdansk]

At 125 W base power, that leaves 0.43 W per core. Which Intel cores work optimally at that level? Heck if you go to 250 W for turbo that is still only 0.87 W per core. You end up in a situation where the cores become highly-inefficient and take even more power to get each unit of the work done. Power that they don't have.

Plus the cost. Yes, going from 26 to 52 cores is just one more tile with a manageable cost. But going to 288 cores with Nova Lake would be 10 additional tiles. Now price is a huge issue.

Plus the physical space. Putting that many cores together with our current nodes puts the cores far apart. Core to core latency would skyrocket.

288 cores might eventually be worthwhile. But we are far, far from that ideal. Especially for consumer parts.

All these arguments apply, on a smaller scale, to the dual tile setup in general.
The point is that I doubt 16/32 is an "ideal" core count for whatever pin count their latest dual channel socket has. It's a product of convenience. They had a 8/16 tile and the easiest composition is two of them.

And so, if Intel does anything to push this SKU over others it's a loss for the majority consumers, really. It isn't complicated.

 

[511]

well it's not tbh 8+16 is going to be the Ultra 5 and yeah the U5 is going to kick U9 285K in the back so hard it would be hilarious and it is the SKU that will sell the most if they don't mess up

 

[dullard]

All these arguments apply, on a smaller scale, to the dual tile setup in general.
The point is that I doubt 16/32 is an "ideal" core count for whatever pin count their latest dual channel socket has. It's a product of convenience. They had a 8/16 tile and the easiest composition is two of them.

And so, if Intel does anything to push this SKU over others it's a loss for the majority consumers, really. It isn't complicated.

It absolutely is unlikely to be the ideal core count. If I were Intel, I would design a 48 core E-only tile that is just about the same size as the 8P+16E tile. That would be far more optimum for those who really need to crunch numbers. (8P+16E) + (48 E) = 72 total cores (plus any LP-E cores). That would be far more powerful. But, yes, out of convenience and mass production, Intel will reuse the 8P+16E tile.

 

[igor_kavinski]

But, yes, out of convenience and mass production, Intel will reuse the 8P+16E tile.

Forgetting internal politics

 

[OneEng2]

It absolutely is unlikely to be the ideal core count. If I were Intel, I would design a 48 core E-only tile that is just about the same size as the 8P+16E tile. That would be far more optimum for those who really need to crunch numbers. (8P+16E) + (48 E) = 72 total cores (plus any LP-E cores). That would be far more powerful. But, yes, out of convenience and mass production, Intel will reuse the 8P+16E tile.

... and this is where I think it makes the most sense.

Make a CPU that is built for low latency (X3D). Make a CPU that is designed for massively parallel loads (Threadripper), make a CPU that is made for the masses and is inexpensive to build?

How about 2 to 4 "super cores", 2 P cores, and 4-8 E cores .... and maybe 4 LPE. So a jack of all trades CPU that all fits onto a sub 100mm2 CCD and has an IOD tile.

Low end has something like 12 cores.

High end has as much as you can fit on 2 chiplets of low end CCD's.

I think the future is going to be more segmented. Gaming CPU vs Business CPU vs Productivity CPU, etc.

 

[dullard]

I think the future is going to be more segmented. Gaming CPU vs Business CPU vs Productivity CPU, etc.

That has been Intel's plan all along. The image below was 5 years ago. More NPU for corporate employees, more graphics for gamers, more compute for creators, etc. Pick and choose based on need. It looks like Nova Lake is finally the start of that.

https://images.anandtech.com/doci/16021/Section%208%20%2821%29.jpg

 

[ondma]

That has been Intel's plan all along. The image below was 5 years ago. More NPU for corporate employees, more graphics for gamers, more compute for creators, etc. Pick and choose based on need. It looks like Nova Lake is finally the start of that.

https://images.anandtech.com/doci/16021/Section%208%20%2821%29.jpg

Lets hope so. The thing is, pretty much everything since maybe 8th gen (I am still using 8700k for gaming) with the exception of Alder Lake, has been mediocre (all the refreshes with only a few hundred mhz clock bump) to disappointing (Arrow Lake) to disastrous (Rocket Lake and 13, 14 gen stability issues). After this track record when they were financially better off, can they finally pull a rabbit out of the hat with all the current cuts, layoffs and financial limitations? AMD did it, but I dont know if lightning will strike twice.