Discussion Intel Nova Lake in H2-2026: Discussion Threads

[jpiniero]

Medusa Halo will, unless AMD changes their ways, have to be on a post RDNA4 architecture.

It doesn't. Remember it's an AI product and not a gaming one.

 

[LightningZ71]

This isn't a Gaming vs professional type issue. AMD still keeps IPs on node families. They don't have an older IP on N3 to implement, and they won't port it forward if they have to implement a new one on a new node anyway.

 

[511]

Medusa Halo will, unless AMD changes their ways, have to be on a post RDNA4 architecture. They don't have an completed N3 family design for RDNA4 as it's N4/N5 only so far. Same for RDNA3/3.5. It's going to have to be whatever comes next, RDNA5/Next/UDNA whatever. If they do add 20% more CUs (to 48 units) and go for a few speed grades faster RAM, it should be a notable improvement in performance over what they currently have.

Yeah 48CU is fine with RDNA 5 the main issue is the memory subsystem on PCB

 

[jpiniero]

This isn't a Gaming vs professional type issue. AMD still keeps IPs on node families. They don't have an older IP on N3 to implement, and they won't port it forward if they have to implement a new one on a new node anyway.

Maybe Medusa is just the same IO die (or maybe just more NPU) but with Zen 6 chiplets instead.

 

[MS_AT]

It doesn't. Remember it's an AI product and not a gaming one.

That is situational marketing spin. It can be usefull if you set your expectations right (dont expect running models bigger than 32GB will be practical) but its nowhere near marvelous like the pr dept would like you to believe. Who knows maybe Medusa Halo and this new Intel chip will be better suited for the job. Still I don't want to hijack the thread. This was already discussed in the Halo thread anyway.

 

[511]

Yeah but anyways what's the guesstimate for the CU Counts for NVL Halo? i am expecting 5-6 Render Slice(6 XE Cores per Render Slice) with Xe3P arch.

 

[jpiniero]

I'll keep this specific to Intel... (or more anyway)

That is situational marketing spin. It can be usefull if you set your expectations right (dont expect running models bigger than 32GB will be practical)

I don't know if OEMs necessarily care. It's really just a (Wall Street) marketing exercise anyway.

 

[OneEng2]

What is the cost?

https://phoronix.com/benchmark/result/amd-epyc-9965-turin-dense-vs-ampereone-arm-192-core-cpu-benchmarks/geometric-mean-of-all-test-results-result-composite-ae9tdvaa1ccb.svgz

There is always a cost to any design. The M4 does what it does very well; however, things it doesn't do can't be ignored in the larger picture:

• No SMT
• Not x86 compatible
• Tied to apple everything
• Not designed well for heavy sustained loads (better at burst of processing power)
• Real world multi-core work suffers (does great on synthetic benchmarks like geekbench)
• No external graphics interface
• No PCI external interface
• No AVX (only proprietary SIMD and limited at that).
• Relatively large die (168mm2) on N3E (Turin D 16c CCD is about 85mm2)

So, in DC, you would have a 168mm2 10 core M4 facing off with an 85mm2 16 core (with SMT) Zen 5c.

Not hard to predict the outcome.

That isn't to say that M4 isn't a good design. It is very good for what it was intended to be used for; however, it is a mistake to assume that it would automatically dominate processors in other markets that it wasn't designed for.

ie, AMD and Intel engineers aren't stupid and without a clue. There are reasons things are done as they are done.

 

[Saylick]

https://phoronix.com/benchmark/result/amd-epyc-9965-turin-dense-vs-ampereone-arm-192-core-cpu-benchmarks/geometric-mean-of-all-test-results-result-composite-ae9tdvaa1ccb.svgz

There is always a cost to any design. The M4 does what it does very well; however, things it doesn't do can't be ignored in the larger picture:

• No SMT
• Not x86 compatible
• Tied to apple everything
• Not designed well for heavy sustained loads (better at burst of processing power)
• Real world multi-core work suffers (does great on synthetic benchmarks like geekbench)
• No external graphics interface
• No PCI external interface
• No AVX (only proprietary SIMD and limited at that).
• Relatively large die (168mm2) on N3E (Turin D 16c CCD is about 85mm2)

So, in DC, you would have a 168mm2 10 core M4 facing off with an 85mm2 16 core (with SMT) Zen 5c.

Not hard to predict the outcome.

That isn't to say that M4 isn't a good design. It is very good for what it was intended to be used for; however, it is a mistake to assume that it would automatically dominate processors in other markets that it wasn't designed for.

ie, AMD and Intel engineers aren't stupid and without a clue. There are reasons things are done as they are done.

Well, hold on there. The M4 die contains a lot of uncore that makes it an apples-to-oranges comparison against AMD's CCD design, which is predominantly a compute die with the bare essentials for die-to-die connectivity. If Apple were to pursue the DC market, I don't see why they wouldn't produce a specific DC family of dies (call the first one D1 or whatever).

 

[dullard]

The M4 die contains a lot of uncore that makes it an apples-to-oranges comparison against AMD's CCD design

Can we please keep the Apple vs. AMD discussion in any other thread but the Intel Nova Lake thread?

 

[LightningZ71]

Maybe Medusa is just the same IO die (or maybe just more NPU) but with Zen 6 chiplets instead.

This was my original understanding, that Medusa would be just a CCD swap and keep the same IOD. Lately though, I've been seeing rumors that the IOD is going to be heavily updated. It'll be interesting to see what finally faces Nova Lake. Their Xe based iGPUs haven't been bad when it comes to performance, and Xe3 is supposed to bring a notable improvement.

 

[poke01]

Can we please keep the Apple vs. AMD discussion in any other thread but the Intel Nova Lake thread?

Moved to the Apple thread

 

[Kepler_L2]

Medusa Halo will, unless AMD changes their ways, have to be on a post RDNA4 architecture. They don't have an completed N3 family design for RDNA4 as it's N4/N5 only so far. Same for RDNA3/3.5. It's going to have to be whatever comes next, RDNA5/Next/UDNA whatever. If they do add 20% more CUs (to 48 units) and go for a few speed grades faster RAM, it should be a notable improvement in performance over what they currently have.

RDNA 3.5+ of Medusa Point is on N3P.

 

[igor_kavinski]

RDNA 3.5+ of Medusa Point is on N3P.

Would it be safe to say that it would hit 3.5 GHz?

 

[poke01]

Please launch, thats a killer setup.

 

[511]

View attachment 127242
Please launch, thats a killer setup.

Yeah also LPDDR5 10670 likely uses MoP

 

[511]

@Kepler_L2 saw your tweet that MDS Halo is getting axed as well

 

[Kepler_L2]

@Kepler_L2 saw your tweet that MDS Halo is getting axed as well

I don't know if it's axed, could just be delayed for LPDDR6 or they're skipping it and going straight to next-gen (i.e Zen7+RDNA6 in 2028 instead of Zen6+RDNA5 in 2027).

 

[511]

I don't know if it's axed, could just be delayed for LPDDR6 or they're skipping it and going straight to next-gen (i.e Zen7+RDNA6 in 2028 instead of Zen6+RDNA5 in 2027).

If it's Zen 7 I doubt it's before H2 28

 

[511]

Anyway H2 27 is Griffin Cove and Golden Eagle

 

[MS_AT]

Please launch, thats a killer setup.

How many EUs are equivalent to one CU? If it is 1 : 1, then it will be really bandwidth starved.

 

[Kepler_L2]

How many EUs are equivalent to one CU? If it is 1 : 1, then it will be really bandwidth starved.

All the Halo configs are similar

Strix Halo 40 CU
N1X 48 SM
NVL-AX 48 Xe Core

 

[511]

All the Halo configs are similar

Strix Halo 40 CU
N1X 48 SM
NVL-AX 48 Xe Core

this is 24 Xe3P cores lol Internally the count is based on legacy EU For some dumb reason so it's like 24Xe3P Cores

 

[LightningZ71]

It seems like Medusa won't gain a lot by doing an incremental upgrade of memory bandwidth and 20% more CU. It'll wind up more memory starved at the top end than it is now. It always made more sense to just swap out the CCDs for Zen6 ones, upgrade the ram by one or two speed bands and clock up the CUs by 1-200mhz. Then do another big upgrade of it for the next memory tech, lpddr6.

 

[DavidC1]

this is 24 Xe3P cores lol Internally the count is based on legacy EU For some dumb reason so it's like 24Xe3P Cores

They said Pantherlake iGPU is 40% faster right? That's with a 50% higher compute unit count, so aside from niche scenarios(where Battlemage is weak at) there isn't much per EU/MHz perf gains.

So 24 Xe3P is essentially B580 in a mobile form factor. Yes it has 20% more units but mobile is slower plus bandwidth is only about 2/3rd.

Looks like from eyeballing and rough search it should be fairly competitive performance-wise with AMD.