Discussion Intel Nova Lake in H2-2026: Discussion Threads

[511]

All these delightfully declarative statements regarding the cancellation of NVL-AX are based on what official communication from Intel again? Or is it just yet another random internet rumor?

Rumor

Maybe due to the terrible PPA. Same issue and similar fate as Battlemage G31. I didn't have any NVL-AX leak before.

Only Intel knows and their PPA issue has been improving look at Xe3(PTL) vs Xe2(LNL)

 

[Khato]

Rumor

Thanks for confirming I hadn't missed something. To be fair, the original existence of NVL-AX is also just based on rumor far as the internets are concerned.

I look forward to seeing how something the size of G31 but two generations newer does in integrated form. We may not be getting any discrete cards of interest for awhile, but if the integrated does well against the future higher-end NVIDIA variants that will likely signal a return to discrete.

 

[511]

Thanks for confirming I hadn't missed something. To be fair, the original existence of NVL-AX is also just based on rumor far as the internets are concerned.

I look forward to seeing how something the size of G31 but two generations newer does in integrated form. We may not be getting any discrete cards of interest for awhile, but if the integrated does well against the future higher-end NVIDIA variants that will likely signal a return to discrete.

The only discreet card planned is Crescent Island for 26

 

[regen1]

Not sure about the fate of NVL-AX but it was/is planned to launch at Computex 2027 or later. Whether it is cancelled or not don't take its current absence on Git/Kernel pages as the definite proof of cancellation. It could be just products getting mentioned as per nearness of launch.If it's been cancelled, so be it.

Oh yes indeed, then it seems cancelled unless it comes much later, even though CRI comes much later than NVL-S they have already included it.

0xD745, TPlatformIndexGt( GENERATION_NVL, GFX_GTTYPE_UNDEFINED, 2 ) }, // NVL-HX

metrics-discovery/instrumentation/metrics_discovery/linux/inc/md_gfx_device_info.h at 1b7f8109ed6eb23aea70112b6be3929b1657a29b · intel/metrics-discovery

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Xe3_LPG/Xe3P_LPM (Panther Lake, NVL-S: Nova Lake S, NVL-U: Nova Lake U, NVL-H: Nova Lake H, NVL-HX: Nova Lake HX, NVL-UL: Nova Lake UL)

gmmlib/README.rst at 5f1c01f46ecbfceec59faef9bf3ba4625fc88fed · intel/gmmlib

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NVL-HX still alive by the looks of it.

Adding this page to those

cm-compiler/clang/compute_sdk/docs/cmcuserguide/platforms.rst at cmc_monorepo_110 · intel/cm-compiler

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All the various listed NVL configs in those pages are Xe3 based. None of these have NVL-H(4+8+4) with Xe3P iGPU mentioned yet which surely is/was planned to release earlier than NVL-AX. (Xe3P_LPM refers to media engine)

The only discreet card planned is Crescent Island for 26

They are saying customer sampling in H2 2026. Actual availability might be end 2026 or H1 2027.

 

[Fjodor2001]

Does Intel plan to do big SoCs with Nvidia?

If that’s the case, I wish them good luck.

There is this rumor about Intel Serpent Lake APU with nVidia Rubin GPU:

Intel's 'Serpent Lake' CPU leaks, its first chip developed in collaboration with Nvidia

Meanwhile, Razer Lake, Hammer Lake and Titan Lake take the fight to AMD.

www.pcgamer.com

”Up front and centre we have RedGamingTech's claims that Intel's first collab' chip with Nvidia will be known as "Serpent Lake". It is, of course, official public information that Intel and Nvidia are collaborating on a generation of future APUs for PCs. So, the basic idea of such a chip is not a stretch. We just haven't had any details as to what that might actually mean.

RedGamingtech describes Serpent Lake as an "APU monster" similar in remit to AMD's Strix Halo chip. It's said to sport Nvidia's next-gen Rubin GPU technology built on TSMC N3P silicon, while CPU tech from Intel's upcoming Titan Lake generation, more on which in a moment. Oh, and it's all supported by LPDDR6 memory.”

Lots of other stuff in that article too by the way.

 

[511]

There is this rumor about Intel Serpent Lake APU with nVidia Rubin GPU:

Intel's 'Serpent Lake' CPU leaks, its first chip developed in collaboration with Nvidia

Meanwhile, Razer Lake, Hammer Lake and Titan Lake take the fight to AMD.

www.pcgamer.com

”Up front and centre we have RedGamingTech's claims that Intel's first collab' chip with Nvidia will be known as "Serpent Lake". It is, of course, official public information that Intel and Nvidia are collaborating on a generation of future APUs for PCs. So, the basic idea of such a chip is not a stretch. We just haven't had any details as to what that might actually mean.

RedGamingtech describes Serpent Lake as an "APU monster" similar in remit to AMD's Strix Halo chip. It's said to sport Nvidia's next-gen Rubin GPU technology built on TSMC N3P silicon, while CPU tech from Intel's upcoming Titan Lake generation, more on which in a moment. Oh, and it's all supported by LPDDR6 memory.”

Lots of other stuff in that article too by the way.

If serpent lake is launching 28-29 fennyman would be the likely GPU Arch

 

[Fjodor2001]

If serpent lake is launching 28-29 fennyman would be the likely GPU Arch

I suppose you mean Feynman. But perhaps that'll be too newly released to be integrated in an Intel APU with Titan Lake CPU?

 

[511]

I suppose you mean Feynman. But perhaps that'll be too newly released to be integrated in an Intel APU with Titan Lake CPU?

i doubt so

 

[Tigerick]

Not sure about the fate of NVL-AX but it was/is planned to launch at Computex 2027 or later. Whether it is cancelled or not don't take its current absence on Git/Kernel pages as the definite proof of cancellation. It could be just products getting mentioned as per nearness of launch.If it's been cancelled, so be it.



Adding this page to those

cm-compiler/clang/compute_sdk/docs/cmcuserguide/platforms.rst at cmc_monorepo_110 · intel/cm-compiler

Contribute to intel/cm-compiler development by creating an account on GitHub.

github.com

All the various listed NVL configs in those pages are Xe3 based. None of these have NVL-H(4+8+4) with Xe3P iGPU mentioned yet which surely is/was planned to release earlier than NVL-AX. (Xe3P_LPM refers to media engine)



They are saying customer sampling in H2 2026. Actual availability might be end 2026 or H1 2027.

Xe3_LPG/Xe3P_LPM (Panther Lake, NVL-S: Nova Lake S, NVL-U: Nova Lake U, NVL-H: Nova Lake H, NVL-HX: Nova Lake HX, NVL-UL: Nova Lake UL)

Hmm, it kinda make sense that Mobile Nova Lake is using same iGPU tile as Panther Lake: Xe3_LPG (4 and 12 Xe3 Battlemage IP) due to same memory interface, ie. 128-bit LPDDR5x.

As for Xe3P_LPG (Celestial IP ), it should be used on upcoming Mobile Razor Lake and Titan Lake. Talking about confusing naming, Celestial IP is next gen GPU architecture. I am expecting much bigger improvement due to LPDDR6 memory interface.

 

[511]

Hmm, it kinda make sense that Mobile Nova Lake is using same iGPU tile as Panther Lake: Xe3_LPG (4 and 12 Xe3 Battlemage IP) due to memory BW, ie. 128-bit LPDDR5x.

Xe3P is different from Xe3 like the difference between Xe3 and 3P is bigger than Xe vs Xe2 .
SIMD32 512 GPR and other stuff

 

[mikk]

The smaller NVL-H tile will use Xe3 from PTL and only the bigger one should use Xe3p on NVL-H, that's why it can be confusing at the moment.

 

[regen1]

Xe3_LPG/Xe3P_LPM (Panther Lake, NVL-S: Nova Lake S, NVL-U: Nova Lake U, NVL-H: Nova Lake H, NVL-HX: Nova Lake HX, NVL-UL: Nova Lake UL)

Hmm, it kinda make sense that Mobile Nova Lake is using same iGPU tile as Panther Lake: Xe3_LPG (4 and 12 Xe3 Battlemage IP) due to same memory interface, ie. 128-bit LPDDR5x.

As for Xe3P_LPG (Celestial IP ), it should be used on upcoming Mobile Razor Lake and Titan Lake. Talking about confusing naming, Celestial IP is next gen GPU architecture. I am expecting much bigger improvement due to LPDDR6 memory interface.

View attachment 136169

Well, most of the NVL(NVL-S/HX, NVL-H(4P+8E+4LPE) with 4Xe3 iGPU, NVL-U/UL) uses Xe3 IP for iGPU but there's also NVL-H(P? 4P+8E+4LPE) with 12Xe3P iGPU based SKUs(tentatively) which is not there yet in git/kernel pages.

To simpify,
NVL-H with 4Xe units config uses Xe3 IP, same IP as PTL-H SKUs with 4Xe config.
NVL-H(P?) with 12Xe units config based SKUs use Xe3p(tentatively).

PTL, that's going to be released at CES should be using Xe3_LPM for media.
NVL is using Xe3P_LPM for media.


Only known Xe3P GPU IP based product(apart from "cancelled/internal use" Falcon Shores) confirmed and having public mentions in git/kernel pages as of now is Crescent Island(Xe3p_xpc/CRI).

 

[regen1]

The smaller NVL-H tile will use Xe3 from PTL and only the bigger one should use Xe3p on NVL-H, that's why it can be confusing at the moment.

Interestingly there seems to be another 4Xe3 tile(newer tape-out) available/used for NVL-H/U though it is functionally kinda same as the 4Xe3 tile in PTL-H/U.

Spoiler

 

[511]

Interestingly there seems to be another 4Xe3 tile(newer tape-out) available/used for NVL-H/U though it is functionally kinda same as the 4Xe3 tile in PTL-H/U.

likely some improvements

 

[jdubs03]

Not bad for a follow up a year later:

https://videocardz.com/newz/intel-xe3p-nova-lake-integrated-graphics-reportedly-20-25-faster-than-panther-lakes

 

[511]

Not bad for a follow up a year later:

https://videocardz.com/newz/intel-xe3p-nova-lake-integrated-graphics-reportedly-20-25-faster-than-panther-lakes

This may be higher cause this must be based on early sample it's going to have issue of not having enough Memory Bandwidth

 

[regen1]

This may be higher cause this must be based on early sample it's going to have issue of not having enough Memory Bandwidth

It could probably be higher than 30% which won't be bad considering memory speeds would be limited by LPDDR5X(likely 10667MT/s, vs PTL's 9600MT/s).
It's new XMX engines(newer data types and likely higher throughput) should be good.
They need to upgrade the XESS image quality.

 

[DavidC1]

This may be higher cause this must be based on early sample it's going to have issue of not having enough Memory Bandwidth

In fact 20-25% would be a disappointment actually. We have Canis coming 2 years later with "15W being similar to 30W", and Xe4 not being on the pipeline until later. So it would be looking at Pantherlake vs Strix Point, except it's flipped around with AMD having the advantage. Also, it depends if 18A actually offers some gains here, then it looks even worse for Xe3P.

Also I know not to trust marketing at a face value. Their claim was that the Xe3 was the small change and Xe3P is the big one. Yet 20-25% is no different than Xe3, because in order to achieve 1.5x at same W, it would need to do 1.2-1.25x better at the same shader count.

Maybe if the Xe3P is indeed that low of a gain, it lends credence to why there's not much leak about Xe4 and the partnership with Nvidia. Xe3P seems to be about the timeline when Pat Gelsinger's influence ends, the same CEO that wanted to prove dGPUs at Intel can succeed.
View attachment 135481
So they are going back down to 8 threads per Xe core with Xe3P when Xe3 is at 10 already?

 

[poke01]

it depends if 18A actually offers some gains here, then it looks even worse for Xe3P.

is the GPU tile on 18A in Nova Lake-H?

 

[511]

is the GPU tile on 18A in Nova Lake-H?

N2

 

[Joe NYC]

N2

N2 for GPU? Seriously

 

[511]

N2 for GPU? Seriously

For only the Xe3P iGPU in NVL iGPU Yes raichu said in a post as well

 

[Joe NYC]

For only the Xe3P iGPU in NVL iGPU Yes raichu said in a post as well

Thanks, I must have missed that. Intel is spending big bucks. I wonder how it turns out.

If memory shortages persist more than a year, it would slightly favor iGPUs, which have better memory utilization efficiency, than mobile dGPUs.

Both Intel and AMD could be winners if they can take the market from at least the low to mid dGPUs and actually be able to gain full revenue from nVidia.

 

[mikk]

N2 makes no sense to me if it's still a 12 Xe core version with the same amount of SIMD units. Isn't N3E cheaper and more than good enough for such a tiny iGPU? +25% is indeed not so great for the "bigger than Xe2 to Xe3 architecture" claim. Assuming there is no shader count and bandwidth increase a big performance uplift would be hard to achieve even with a bigger architecture change. PTL comes with 50% more units and much higher GPU clock speed versus LNL and versus ARL it is Xe1+ vs Xe3.

 

[regen1]

+25% is indeed not so great for the "bigger than Xe2 to Xe3 architecture" claim. Assuming there is no shader count and bandwidth increase a big performance uplift would be hard to achieve even with a bigger architecture change. PTL comes with 50% more units and much higher GPU clock speed versus LNL and versus ARL it is Xe1+ vs Xe3.

It will likely be higher. 25% doesn't seem that bad with all the restrictions. Even similar gains as Xe3 will dispel "Xe3 is a much bigger change than Xe3p is" rumors.
For Generation after NVL they will have options to improve performance: more Xe cores, LPDDR6, possible clock gains. PPA improvements will help.


For CRI, from OCP 2025 image and some commits, it seems it could be either 6XVEs or 12XVEs per Xe (?). It would have just compute, XMX engines and media engines, no GFX stuff(RT, raster). For consumer versions the Xe3p config(no. of XVEs per Xe) could be different. XMX engine for consumer version might be somewhat different as well wrt throughput and/or data type support.