Discussion Intel Nova Lake in H2-2026: Discussion Threads

[poke01]

If Intel actually wants to make use of more cores

 

[dullard]

It's 1t it's never power limited on desktop (anywhere, really).

No you don't.

You can't, Vmax is one for all.

I see you are now contradicting yourself, on the same page even. Good Job.

 

[adroc_thurston]

I see you are now contradicting yourself

No?
I think you need better reading comprehension or at least the basic understanding of how semiconductors work.

 

[dullard]

I think you need better reading comprehension or at least the basic understanding of how semiconductors work.

Please explain it better for me.

Since we do not know power levels in the leak, they could be passively cooled, air cooled, water cooled, liquid nitrogen cooled, etc. It could be at 15W or 320W or someplace in between. A single core in 1T could easily consume 20W, 30W, or more. For 1T, that wide variety of power levels and wide variety of possible cooling gives us a wide range of possible frequencies. Way more range of frequencies than would give the +10% 1T performance that we are discussing. We are talking easily a 4X range of frequencies, if not 5X depending on how the test was performed. So, without knowing any more information of how it was run, a 4X range of frequencies to get a +10% performance increase gives us no real estimate of IPC.

If we knew the test was iso-power then you'd have a point. But we don't.

But for MT, the possible range of frequencies is drastically smaller. This is because the range of power that can be given to each core is much tighter. You can't say give 20 W or 30 W of power to each cores because that would blow the power budget. Heck, you couldn't give 7 W each* in 320 W total PL2. One could pretty accurately estimate the power (plus or minus a bit), the frequency, and thus the IPC.

* Note: P cores would have different power levels than E cores, but separating them out in this paragraph made it too complex to explain to you.

 

[adroc_thurston]

A single core in 1T could easily consume 20W, 30W, or more.

It can only consume what it can consume at max voltage.
Which for N2 is 1.2v-ish. Not much.

Way more range of frequencies than would give the +10% 1T performance that we are discussing

There are none, DT parts clock close-to or at Vmax.

 

[poke01]

There’s now rumours that slide is for Lunar lake vs Panther lake. Which does seem likely

 

[adroc_thurston]

There’s now rumours that slide is for Lunar lake vs Panther lake.

It is NVL-S.
Panther Lake has 0 to negative % of 1t uplift over ARL/LNL.

 

[poke01]

It is NVL-S.
Panther Lake has 0 to negative % of 1t uplift over ARL/LNL.

Ouch

 

[adroc_thurston]

Ouch

Yeah the selling points for PTL are the iGP and some of the LNL BL goodies.

 

[reaperrr3]

what da hell.
If this is what they need for 60% moar nT then Atom guys need to commit sudoku too.

I'm not sure what's so surprising about this.

Mediocre multi-core scaling of many applications aside, we're talking about 100% moar cores (especially P cores), presumably with notably more transistors for IPC than their LNC/SKM predecessors, on a process that brings what, 20% power savings at iso clocks at iso transistor count at iso voltage vs. N3B?
The moment Intel went with 2 CPU chiplets, it was kinda clear that this thing would be severely power-constrained under all-core loads.

Makes me wonder whether it would've been smarter to go with 2x 6+16 instead.
16 P cores @ desktop clocks are probably going to eat those PLs for lunch even without 32 "E" cores sipping away some of that power.

 

[adroc_thurston]

I'm not sure what's so surprising about this.

It's like twice the hardware, that alone should be a massive net win given you can run the horde at a far more favourable v/f breakpoint.
RPL/ARL-S have pretty aggressive boosting for atoms in particular.

 

[DavidC1]

Now not so. They need a good core to bounce back and clocks are a part of that. The best scenario would be to get gains from architecture and clocks and process node.

That's exactly my point, since we already have the data. Increased clocks would mean no uarch gains. It's favorable to Intel not to have increased clocks.

Let's say it's a 7GHz part and it's 25% faster? Why is that something to be celebrated? Do we expect the successor to be 7.5GHz? And then 8GHz after that? You guys do know the world record is 9.1GHz using Raptorlake cooled down to -250C? Officially the non problematic max clock is 5.7GHz right now.

It doesn't even make sense to expect 6.5GHz easily. The last time they got a big gain they did that by eliminating overclocking. We have air coolers with better performance than water coolers of 15 years ago. Water cooling used to be almost in the realm of exotic cooling, that's how they used to push clocks!

Zen6: 10%+ IPC
NVL: >10% ST Performance

On the surface, this doesn't look terrible for Intel. If Zen 6 doesn't get increased clocks, and Novalake's >10% gets to be say, 14%, then again it's neck and neck. Maybe they are 2-3% slower in ST but significantly better in MT.

It's not a slam dunk, and I think that's more of the disappointment than anything.

 

[poke01]

It’s still too early things CAN change. It’s not June of 2026. I will remain optimistic

 

[adroc_thurston]

but significantly better in MT.

Where

 

[Io Magnesso]

But it certainly didn't even say "NOVA LAKE" on that leaked slide.
Well, if the leaked slide file had the name Nova Lake, I can't deny it...

 

[Io Magnesso]

Where

It can't be helped, because his remarks are always funny
It's not surprising that you are confused

 

[511]

what da hell.
If this is what they need for 60% moar nT then Atom guys need to commit sudoku too.

seppuku*

It's 150W PL1 and 320W PL2

So 150W PL1/320W PL2 not sustained 320W PL2? vs 125W PL1 and 250W PL2?

 

[Io Magnesso]

seppuku*

So 150W PL1/320W PL2 not sustained 320W PL2? vs 125W PL1 and 250W PL2?

Yes, the ECore team doesn't need to commit seppuku It's like a kamikaze attack on talented people.
It's the Cove team that should commit seppuku

 

[511]

It is NVL-S.
Panther Lake has 0 to negative % of 1t uplift over ARL/LNL.

Lol so they F***** cougar cove as well

 

[adroc_thurston]

Lol so they F***** cougar cove as well

Oh no, that's an 18A issue.

 

[jdubs03]

Oh no, that's an 18A issue.

Yup. The constant disappointment and morass continues.

https://www.reuters.com/business/retail-consumer/intels-new-ceo-explores-big-shift-chip-manufacturing-business-2025-07-02/

 

[511]

Yup. The constant disappointment and morass continues.

https://www.reuters.com/business/retail-consumer/intels-new-ceo-explores-big-shift-chip-manufacturing-business-2025-07-02/

Should read the article and it's total nonsense like his previous TSMC Intel merger.

 

[branch_suggestion]

seppuku*

It's a meme you dip.

 

[Io Magnesso]

Oh no, that's an 18A issue.

That's amazing, you know it's a 18A problem
Why did you find out that Intel 18A was the cause?

 

[poke01]

Oh no, that's an 18A issue.

You know that N1X chip from Nvidia might not actually be behind PTL then.