Discussion Intel Nova Lake in 2026: Discussion Threads

[adroc_thurston]

I’m assuming the the other tiles are 18A

Nope.
18A is no good for analog stuff until 18A-P.

 

[511]

So up to ~180mm2 of N2 die. Not bad.

Just my guesstimation

I’m assuming the the other tiles are 18A?

The SoC is 18A makes sense cause it contains 4 LP-E Arctic wolf cores same as the compute tile they won't have redo the design on a third node.

 

[511]

Nope.
18A is no good for analog stuff until 18A-P.

Well the SoC or should I call it HUB is 18A

 

[Io Magnesso]

Was there a part that uses analog in the SOC tile?

 

[Io Magnesso]

So up to ~180mm2 of N2 die. Not bad.

I’m assuming the the other tiles are 18A?

Hmm? So you think the N2 version will be made in a larger size?
Assuming it will be placed in two
I don't know the details, but I think the one in this image is the maximum configuration using the tiles made with TSMC N2.

 

[Io Magnesso]

It's costly to go out of your way to create a large cache (SRAM) in the cutting edge process...
For the time being, there should be almost no conversion of the bitcells around the area until the CFET comes out.

 

[511]

Was there a part that uses analog in the SOC tile?

Memory controller Media engine and some other stuff.

 

[Io Magnesso]

Memory controller Media engine and some other stuff.

I agree I forgot