Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DavidC1]

I’ve no such site

😂🤣😂

Sorry. I was confusing you with @AshlayW

Question - Please can someone tell me what Hawaii's rate of FP16 precision is please

I am writing a tech blog and I am trying to find out what speed Hawaii graphics processor (I.e R9 290X) can perform Half-precision calculations at, and is it throttled in the Radeon gaming cards. I can't find it anywhere by my Google-fu skills are very lacking Thanks

forums.anandtech.com

 

[DavidC1]

Trip down memory lane...

The Pentium back end.
U and V INT pipes and A FP pipe. No scheduler, no OoO but those clever engineers came up with a "controller" to send a pair of instructions in program order down the U pipe to be executed at the same time... boom! Superscaler with no OoO!

The U and V pipe config is still used today. That's why the decoders are referred to as 4-1-1-1 or something like that. It means the first decoder is "complex" and can decode instructions that can split up into 4 uops, and the other ones can do 1 and has to send them to the slow as molasses microcode. This is likely to reduce complexity.

The x86 world's advancements largely resolve around trying to solve the decode issue. Clustered decode is likely that solution. Note, it isn't that big of an issue today. Look at how much that section takes, it's a fraction of maybe 20% and ARM does decoding too, just not variable length decode.

K7 ended up better, but it had flaws like the "glued" ALU/AGU blocks and its L2 cache. But its L1 cache was large and low latency so I have to disagree it was due to core design. As for as .18u, AMd did OK with it. It was its crappy SSE performance that probably hurt it more. I would sooner say their iniital .13u process (T-bred A) that sucked.

Actually L1 is extremely close to the core and affects things like how you layout the core and such:

Silvermont, Intel's Low Power Architecture - Page 2 of 8 - Real World Tech

Silvermont is Intel’s first CPU core tailored for power efficient applications such as smartphones, tablets, and microservers. The 22nm microarchitecture features updated instruction set extensions, full out-of-order execution with a tightly coupled L2 cache, aggressive power management, and a...

www.realworldtech.com

L1 is fundamentally different from the other levels:
-In Atom based uarchs, the instruction boundary is stored in the L1 Instruction cache
-They are separated into Instruction and Data
-The Load and Store performance related to the core directly affects L1 cache throughput
-The fetched instructions are stored in the L1 caches, so are the decoded ones.

When K7 came out sites reported it had an advantage over P3 even in IO throughput, and it also had a fully pipelined FP unit when P3 didn't. The predecessor struggled to clock and Intel had an advantage but K7 just passed by, meaning everything improved including circuitry not just uarch. P3 being based on an older uarch is also proven by how Tualatin topped out at 1.4GHz, while Pentium M pushed all the way to 1.8GHz, despite also having a low power focus.

 

[Josh128]

18A I think only needs to be competitive with N2 for Intel to really stay in the game. Let me put some numbers to what I'm thinking.
If Zen 6 does indeed hit 6.4GHz on a single core and Nova Lake is stuck at 5.7GHz ST then that is not competitive.
Or if Zen 6 is hitting 65,000 in CB R23 at 200W and Nova Lake requires 275W then that is not competitive.
They need to be around 5% in the important metrics.

Now things get "fuzzy" with process and architecture because they are inexorably intertwined. A really great architecture can "cover" for a not so good node, and vice-versa. If 18A has great density and they can get all of those core crammed into a cost effective tile then Nova Lake can do well MT based on just having a transistor advantage.

Max ST frequency, max MT frequency/power/heat, ST IPC, lots of unknowns still. AMD has been firing on all cylinders since they moved to TMSC because for the first time they had the process advantage, which Intel has relied on previously. AMD really only has one ball in the air, architecture, TMSC handles the other one for them. Intel has two balls in the air. It can be a great show IF you don't drop a ball.

I think Panther Lake is looking to be a rather big technical success for Intel. 5.1GHz on 18A ain't bad for mobile. Efficiency looks to be very good if not great. iGPU is very, very good with no reports (so far) of major driver issues (Alchemist R&D paying dividends), and CPU performance did creep ahead of Lion Cove, which has the advantage of being desktop in terms of memory subsystem.

If they can get the clocks competitive with Zen 6 (whatever that will be) and pull another 5% out of Cougar Cove and catch up in gaming this could be fun. Yeah I know, lots of "ifs."

Clocks dont need to be competitive with Zen 6 if IPC increases another 10% from Panther Lake. Vs Zen 5, Panther Lake is already +10% ahead in integer IPC and tied in fp IPC. They pull off a +10/+10 in Nova Lake and they can afford to be down 10% in clocks and still be competitive.

 

[Hulk]

Clocks dont need to be competitive with Zen 6 if IPC increases another 10% from Panther Lake. Vs Zen 5, Panther Lake is already +10% ahead in integer IPC and tied in fp IPC. They pull off a +10/+10 in Nova Lake and they can afford to be down 10% in clocks and still be competitive.

Let's unpack this.
I think you are referring to the SPEC 2017 results?
They showed Cougar Cove +10% over Zen 5 for INT and even for FP.

I wonder how that +10% INT and 0% FP will translate into applications and benchmarks we know and love? I wish we have an apples-to-apples comparison of Cougar Cove and Lion Cove to get a little more perspective.

Let's say Zen 6 is 5% behind Coyote Cove. That means Nova could stand a 5% regression in frequency compared to Zen 6. That would be like 6.3GHz for Zen 6 and 6GHz for Coyote Cove.

That's a possible situation. But a worst case for Intel would be Zen 6 shows +5% IPC and frequency over Coyote Cove. That is possible as well. As I've been saying all of this silence from AMD might indicate a quiet confidence. You know how you don't have to talk it up when you have the goods?

If I had to put money on it we'll be seeing another neck-to-neck race at the top of the stack.

 

[Hulk]

The U and V pipe config is still used today. That's why the decoders are referred to as 4-1-1-1 or something like that. It means the first decoder is "complex" and can decode instructions that can split up into 4 uops, and the other ones can do 1 and has to send them to the slow as molasses microcode. This is likely to reduce complexity.

But isn't the difference that P5's U/V pipes must retain program instruction order? I mean for the change in terminology. When OoO scheduling become possible with P6 Intel abandoned the U/V nomenclature and moved to execution ports and execution units to describe the back end.

For example, Broadwell was 3+1, 3 simple and 1 complex decoder so it was referred to as "4 wide." It could either decode 4 uops/cycle using the legacy decoders or pull 4 uops/cycle from the uop cache via Loop Stream Detector (LSD). Either way 4 wide.

But then with Skylake Intel is calling it "5 wide" even though the decoders are still 3+1. But, the bandwidth of the uop cache was increased to 6 uops. I have been under the impression (probably totally wrong!) that they got "5" as an average of 4 from the legacy decoders and 6 from the uop cache for an average of 5. Or is there some case where the complex decoder can fuse two uops into one or something clever like that going on that changed from Broadwell to Skylake? The only thing I'm seeing different in the back end that would make Skylake wider than Broadwell is the 6uops/cycle uop cache bandwidth increase.

This has been something I've never quite understood fully.

 

[reaperrr3]

Clocks dont need to be competitive with Zen 6 if IPC increases another 10% from Panther Lake. Vs Zen 5, Panther Lake is already +10% ahead in integer IPC and tied in fp IPC. They pull off a +10/+10 in Nova Lake and they can afford to be down 10% in clocks and still be competitive.

I'm 99% positive boosting integer IPC was the focus of Zen6 and will be where most of the 10%+ IPC increase will be coming from.

MLID says that according to one of his sources (yeah yeah, I know, it's MLID, but at least for Zen IPC leaks his track record is decent enough) that FP IPC will only increase by about ~6%, yet the (proven to be legit) core roadmap slide leak clearly stated 10%+ in total IPC increase, so I'd wager AMD aimed for over 10% INT IPC increase.

Zen5 massively boosted FP, especially the PRF which was flat out doubled over Zen4, while int only got a measly 16 extra PRF entries despite 50% more ALUs.
adroc mentioned the IntPRF is a bottleneck now, but that also means notably increasing the IntPRF in Zen6 is a low-hanging fruit that may yield fairly big gains.

Anyway, let's say +6% in FP and +14% in INT for an average of +10%, that would put Zen6 ~5% ahead of PTL in average IPC.
If NVL only added 10% over PTL in both, the IPC advantage would be only like 5% over Zen6. It'll need more than that to make up for a 700 MHz deficit.

And don't forget: Higher IPC in specific workload types is not the same as clockspeed.
10% higher clocks are almost guaranteed to uplift perf more uniformly than 10% "higher IPC", which is actually fairly workload-dependant.

Last but not least, I'm still not convinced that Zen6 will top out at only 6.4 GHz. I consider that a conservative assumption, given it's a jump from N4P to N2P. The combined electrical improvements TSMC lists for N3E/P and N2P are decidedly bigger than the improvement from N7P to N5P was, and Zen4 jumped 800 MHz in max clock.
And no, the increased core count per CCD won't have much of an impact on that imo, because if I were AMD, I'd rather keep the base clock / all-core turbo modest to leave enough headroom for high 1C/2C turbo clocks.

 

[regen1]

B390 compared with some dGPUs(desktop) in some games.

Arc B390 vs. Desktop-Grafikkarten im Test: Intel überrascht mit MFG

Wie gut ist die Arc B390 und was kann Intels neue Multi Frame Generation? PCGH hat es ausführlich getestet.

www.pcgameshardware.de

View attachment 137425

For this particular test it was more performant, quieter in "Balanced" mode.

"Performance" mode scored better in retest.

 

[DavidC1]

For example, Broadwell was 3+1, 3 simple and 1 complex decoder so it was referred to as "4 wide." It could either decode 4 uops/cycle using the legacy decoders or pull 4 uops/cycle from the uop cache via Loop Stream Detector (LSD). Either way 4 wide.

Yea but Skylake only had 4 physical decoders.

Intel Architecture Day 2021 Golden Cove Front End - ServeTheHome

Intel Architecture Day 2021 Golden Cove Front End

www.servethehome.com

For example, Broadwell was 3+1, 3 simple and 1 complex decoder so it was referred to as "4 wide." It could either decode 4 uops/cycle using the legacy decoders or pull 4 uops/cycle from the uop cache via Loop Stream Detector (LSD). Either way 4 wide.

It can actually to 4+1+1+1, meaning 7 total. And all SIMD since Sandy Bridge or something could be decoded in all of the decoders. 4-wide means it can do 4 simultaneously. The numbers indicate how complex of an instruction it can handle, not throughput. So the first decoder can handle instructions that decode to 4 micro ops, and the rest can only handle that decode to 1 micro op, but you can use all at the same time. The case where it decodes into more than 1 micro op isn't common that's why it's just called 4-wide.

So,
4 = 1-wide
4+1 = 2-wide
4+1+1 = 3-wide
4+1+1+1 = 4-wide

But then with Skylake Intel is calling it "5 wide" even though the decoders are still 3+1. But, the bandwidth of the uop cache was increased to 6 uops. I have been under the impression (probably totally wrong!) that they got "5" as an average of 4 from the legacy decoders and 6 from the uop cache for an average of 5.

It's just what I call "technimarketing". Sounds genuine but tainted by marketing team.

I'm 99% positive boosting integer IPC was the focus of Zen6 and will be where most of the 10%+ IPC increase will be coming from.

MLID says that according to one of his sources (yeah yeah, I know, it's MLID, but at least for Zen IPC leaks his track record is decent enough) that FP IPC will only increase by about ~6%, yet the (proven to be legit) core roadmap slide leak clearly stated 10%+ in total IPC increase, so I'd wager AMD aimed for over 10% INT IPC increase.

"Integer" basically means overall uarch, so if you aim x % for Integer, you'll get that in everything, meaning in AI, in Integer, in FP, whatever you throw at it. Integer is the hardest part to get. FP has roots in accelerators and can be boosted further by other means, and often gets greater gains from additions that are meant for Integer workloads.

 

[DrMrLordX]

Clocks dont need to be competitive with Zen 6 if IPC increases another 10% from Panther Lake. Vs Zen 5, Panther Lake is already +10% ahead in integer IPC and tied in fp IPC. They pull off a +10/+10 in Nova Lake and they can afford to be down 10% in clocks and still be competitive.

Isn't Nova Lake also using Cougar Cove?

 

[DavidC1]

Isn't Nova Lake also using Cougar Cove?

No, Novalake is Panther Cove or Cougar Cove with the E core being Arctic Wolf. @511 knows the P core name better.

 

[DrMrLordX]

No, Novalake is Panther Cove or Cougar Cove with the E core being Arctic Wolf. @511 knows the P core name better.

I thought Panther Cove was just the old name for Cougar Cove before Intel changed it . . .

 

[511]

N2 is a better node otherwise Intel wouldn’t use it for higher end SKUs.

It has higher PPA than 18A for sure It was clear from the choice for 8+16/8+16 bLLC Tile

In fact Intels 48 core CPU wouldn’t be possible on 18A.

64 Core DMR Compute Tile wants to have a word with you

 

[511]

No, Novalake is Panther Cove or Cougar Cove with the E core being Arctic Wolf. @511 knows the P core name better.

I thought Panther Cove was just the old name for Cougar Cove before Intel changed it . . .

It's a mess of naming but Panther Cove is the core in diamond rapids and coyote cove is the client version of Panther Cove.

E cores is arctic wolf.

Both are proper Tock

 

[poke01]

64 Core DMR Compute Tile wants to have a word with you

Not sure if those cores can reach 6GHz+ which is important for desktop on 18A

 

[511]

Not sure if those cores can reach 6GHz+ which is important for desktop on 18A

This is 18AP but I doubt they will doing 6 GHz these are used to make 256C SKU also 48Cores in nova composed of 2 8+16 Tiles same as ARL it's not a single 16+32 die.
Maybe they can make the do 5.5 we will know though cause the 4+0+4 SKU is 18AP

 

[DavidC1]

Zen5 is a 6k entry macro-OP cache.
Each entry is 1-4 fused ops iirc.

And it's on N4, while P4 is on 0.18u.

The 12Kuops on Willamette is 80-100KB in size. An absolute monster since it's core stuff. It would be considered big today for a uop cache.

I think Intel "wasted" lot of good engineers on the P4. Many fantastic stuff, driven by wrong ideals. Also while @igor_kavinski wants 18A Pentium 4, I'd like everything in Prescott WITHOUT the 31 stage pipeline, stay at 20 like the predecessor. 20-30% extra perf/clock would have made things look a lot different.

 

[Abwx]

Let's unpack this.
I think you are referring to the SPEC 2017 results?
They showed Cougar Cove +10% over Zen 5 for INT and even for FP.

In spec int the 358H with 8533 RAM is at the same level as a cut down cache KRK AI 350 using 5600 RAM, what about if RAM speeds where the same, so from where did you pull those 10%.?.

As for FP is your reference Cinebench.?.
Because in all other renderers Zen 5 has better ST IPC than the 285K.

Edit : At 5.1 GHz the 9950X would do 11.27, that s 9.4% better than the 358H, seems
that you got your numbers completely inverted.

 

[Hulk]

In spec int the 358H with 8533 RAM is at the same level as a cut down cache KRK AI 350 using 5600 RAM, what about if RAM speeds where the same, so from where did you pull those 10%.?.

As for FP is your reference Cinebench.?.
Because in all other renderers Zen 5 has better ST IPC than the 285K.

I pulled them from these, which are in this thread.
Also, Lion Cove seems to be a little better than Zen 5 in CB.

 

[Abwx]

I pulled them from these, which are in this thread.
Also, Lion Cove seems to be a little better than Zen 5 in CB.
View attachment 137877

I edited my previous post, at 5.1GHz the 9950X would be 9.4% faster than the 358H in Spec, beside Cinebench is an exception, it s the olny renderer where intel has better ST than Zen 5, in all other renderers without exception Zen 5 has better ST IPC, so that s just cherry picking what is most favourable to Intel while ignoring scores of other tests.

Edit : The 358H is only 4.8GHz, so that s only 3% better in Spec for the 9950X clock/clock, but the former has much faster RAM, 52%, to begin with.

 

[Hulk]

I edited my previous post, at 5.1GHz the 9950X would be 9.4% faster than the 358H in Spec, beside Cinebench is an exception, it s the olny renderer where intel has better ST than Zen 5, in all other renderers without exception Zen 5 has better ST IPC, so that s just cherry picking what is most favourable to Intel while ignoring scores of other tests.

Edit : The 358H is only 4.8GHz, so that s only 3% better in Spec for the 9950X clock/clock, but the former has much faster RAM, 52%, to begin with.

I have no dog in this hunt!
I'm all for Intel and AMD.

Good points!

 

[511]

Edit : At 5.1 GHz the 9950X would do 11.27, that s 9.4% better than the 358H, seems

9950X has like 32MB L3 vs 18MB for PTL spec is sensitive to cache and mem latency alongside the cores as well

 

[Josh128]

Let's unpack this.
I think you are referring to the SPEC 2017 results?
They showed Cougar Cove +10% over Zen 5 for INT and even for FP.

The SPECfp results posted here show Cougar Cove and Zen 5 have identical fp.

 

[msj10]

64 Core DMR Compute Tile wants to have a word with you

DMR compute tile is 16 cores.

 

[Nothingness]

The SPECfp results posted here show Cougar Cove and Zen 5 have identical fp.

Which is exactly what Hulk wrote

 

[511]

DMR compute tile is 16 cores.

no? are we sure that's what i thought initially but it ain't