Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+4+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Khato]

Any 18A yield discussion that doesn't include the opening of fab 52 is quite lacking.

Oh, there hasn't been an announcement or confirmation of fab52 PTL production yet? Guess that would also be on the menu for the earnings call then.

 

[Doug S]

Okay, you want to play that game? Then state a number. What's the 18A yield on either the PTL 484 or 404 die? Or would you prefer to tell us how many PTL parts Intel has shipped?

His response would be the usual "trust me, bro"

 

[DKR]

• PTL shipping expectations (example 1 million units by end of 2026)

FYI, that example number is too low. Just for comparison, Meteor Lake shipped roughly 18-19 million units in 2024 (launched in December'23).On CES 2025, they said they shipped >20 Mu of AI PCs with 1.5Mu contribution from LNL in Q4'24. Their current target is to ship 100Mu AI PC (MTL, ARL, LNL & PTL) in 2024 & 2025 combined which the management said they will be able to meet that target. I expect them to ship at least 20Mu of PTL in 2026 same as MTL (likely will be higher if they catch the Windows 11 refresh tailwind bar the memory prices headwinds).

 

[poke01]

Sorry, I mean this SKU. I can't remember the numbers
View attachment 137055
Yields may be impacting things. But I'm not sure it is a big issue. 200MHz miss around launch is not a huge concern. 288Vs were near mythical too and that wasn't Intel fab.

It’s not the frequency I’m worried abou. Intel cannot fab as many 484 dies hence the delay or OOS.

 

[Khato]

Yeah, frequency is only an issue for the top bin as usual. Same story as ARL there.

There's no question that Intel launches aren't the same as they were 10+ years ago where they had 2-3 months worth of production stockpiled before launch. Their launches are still a far cry from what we see done by their competition though where it can take months for initial laptops to be available. I'd guess PTL launch volume is somewhere around 1Mu.

 

[adroc_thurston]

Yeah, frequency is only an issue for the top bin as usual.

It's the issue for all >4.7G bins.

 

[regen1]

Their launches are still a far cry from what we see done by their competition though where it can take months for initial laptops to be available

Yeah, Strix Point had such poor availability(just a few Asus models) for quite some period after the launch(all with a mature node, btw).

May be some supply issues can happen but RAM situation(DDR5 and esp. high speed LPDDR5X) could potentially impact availability and sales more but that would affect most OEMs(and both x86 vendors) although to a varied degree.

 

[Khato]

It's the issue for all >4.7G bins.

No it isn't. If you want to claim it is, then what are the bin splits for the 368H part?

 

[adroc_thurston]

No it isn't.

yeah it is, we're about to have #fakeboost 2, revenge of 2019 all over again.

then what are the bin splits for the 368H part?

you know well enough that begging gets you *nothing* and yet you still do it. why even.

 

[gdansk]

Intel has made difficult to ship SKUs. 288V was nearly vaporware. And that wasn't a yield problem with N3B.
I really do not think we can deduce yield information from the lack of availability of top SKUs especially near launch.

 

[adroc_thurston]

I really do not think we can deduce yield information from the lack of availability of top SKUs especially near launch.

you can deduce it by not having any of the >4.7G SKUs hold the rated 1t boost.

 

[Khato]

you know well enough that begging gets you *nothing* and yet you still do it. why even.

Curious definition of begging. Here I thought you'd appreciate the opportunity to demonstrate to everyone that you have factual information. Here's another opportunity to prove you know something other than hearsay internet rumor - what process revision is Intel currently running for PTL?

Regardless, for anyone who prefers reality to delusion, bin splits are just fine for the 368H. And they'll be even better with the next minor process revision.

 

[adroc_thurston]

Regardless, for anyone who prefers reality to delusion, bin splits are just fine for the 368H.

they're so fine it never actually hits 5G.
Curious definition of 'fine' but whatever I guess.

 

[regen1]

Any 18A yield discussion that doesn't include the opening of fab 52 is quite lacking.

Initial 18A production in the Oregon research fabs did have low yields a year ago, probably under 20%. This is common for new nodes. Yields then go up. Once fab 52 started 18A production, you can't just use the Oregon fab research yields in discussions.

Intel said 18A yields were going up 7% per month. https://www.tomshardware.com/pc-com...eals-and-cutting-edge-18a-process-is-on-track The latest analyst statement was "over 60%" for 18A yield. https://www.investors.com/news/technology/intel-stock-intc-could-become-number-2-chip-foundry/

Is this the 70% to 80% that TSMC gets? No. Is over 60% abysmal or "toiletbowl-tier"? No. Would we like a detailed list of yield on every size chip on 18A? Of course, but we'll never get that type of info.

18A isn't some broken node like Intel 10nm was but that "7% per month" yield improvement comment from John Pitzer is unclear about what he is claiming that on. Is it like absolute or relative, (like 10+7= 17 or 10+0.7=10.7) ? On what die size (Is he talking about something like 750mm^2 die) ?, etc.
Tomshardware(Anton Shilov) seems to project it in absolute terms which seems iffy/sketchy.

 

[regen1]

This is very concerning Dell has removed the X7 12Xe core of the LCD XPS 14 and 16.

It now starts at $1599 for the ultra 5 4Xe core.

Dell XPS 14-inch Premium Lightweight Laptop with Intel Core Ultra | Dell USA

Shop the XPS 14 ultra-thin & light all day performance laptop featuring Intel Core Ultra Processor & Intel Arc graphics.

www.dell.com

Is there not enough stock? I thought Panther lake was ramping well.

Upgrade break-down is interesting.
U5 325(4+0+4 and 4Xe3) to X7 358H(4+8+4+12Xe3) is charged 100$ less than 16GB 7467MT/s to 32GB 9600MT/s. Bit weird times for PC guys.

 

[511]

Upgrade break-down is interesting.
U5 325(4+0+4 and 4Xe3) to X7 358H(4+8+4+12Xe3) is charged 100$ less than 16GB 7467MT/s to 32GB 9600MT/s. Bit weird times for PC guys.

That RAM price looks reasonableat this point of time can't believe I said that

 

[dullard]

18A isn't some broken node like Intel 10nm was but that "7% per month" yield improvement comment from John Pitzer is unclear about what he is claiming that on. Is it like absolute or relative, (like 10+7= 17 or 10+0.7=10.7) ? On what die size (Is he talking about something like 750mm^2 die) ?, etc.
Tomshardware(Anton Shilov) seems to project it in absolute terms which seems iffy/sketchy.

Time to use a little thought. If the yield goes from "10% to 20%" to "over 60%" in less than a year, do you think the increase was 7% per month or 0.7% per month? Really think hard about it.

And as I said, you'll want yield numbers on all die sizes but you won't get that info. Of course yield drops with die size. You can go off the defect rates (0.2 defects per cm^2) in the links that I provided to get pretty good yield estimates for different die sizes though. Thus the average 750 mm^2 die will have 1.5 defects. Parametric yield will drop at that size (CPU may be functional but not with all cores or not at max frequency, etc.)

 

[DavidC1]

There's a Walmart laptop with 4+0+4 config for $999. The price seems to be $200 higher across the board driven by the RAM cost increase.

I'd guess PTL launch volume is somewhere around 1Mu.

Yea, 1 million units per year would be a catastrophe for Intel.

 

[511]

Yea, 1 million units per year would be a catastrophe for Intel.

Think he meant the launch volume as the initial volume not for year.

 

[DavidC1]

Think he meant the launch volume as the initial volume not for year.

The metric I usually rely on is design wins. 300-500 is a typical number. Skylake they quoted 700 across all segments.

 

[regen1]

Time to use a little thought. If the yield goes from "10% to 20%" to "over 60%" in less than a year, do you think the increase was 7% per month or 0.7% per month? Really think hard about it.

"Yield percentage" numbers without stating Die size is as good as useless.
That was also a point.

If the yield goes from "10% to 20%" to "over 60%" in less than a year, do you think the increase was 7% per month or 0.7% per month? Really think hard about it.

1. Didn't say the increase was 7% or 0.7%, just stating it's unclear. Could've also used 50+7=57(absolute) or 50+3.5=53.5(relative) as example. Some are inferring (Intel rep's statement) as absolute increase, not sure it should be taken as that.

2. Where is 10-20% yield number coming from for less than a year, what die size and other related stuff(parametric and packaging yield included? , etc.). And how are we jumping to 60%+, i.e. +40-50% in absolute terms in less than a year?
10% yield(or such low numbers) claims for client class(say 100-200mm^2 )product series as a whole at about a year before HVM have been debunked many times in EoY 2024 and in 2025 by the likes of Ian Cutress, Pat and others. While 60%+ yields for those class of product-line as whole at this stage looks feasible I am not sure it increased from 10% to those numbers within a year. 7% per month (or 20+% in a quarter?) absolute increase seems scarcely believable for any part of the curve(for those class of die sizes).
Yes, 10-15% yield or so for a very large die is possible. That's why I mentioned something like 750mm^2, given the progress of Intel defect rates may be an optimistic scenario can put those(+7% per month absolute) kinda numbers for that large die for a period.
Anton's and other journos' extrapolation here seems iffy.
But he also did wrongly infer and had people believe N2 having quite significant SRAM bit cell size lead over 18A which turned to be false at ISSCC 2025.

Spoiler: Rough Calc

Let's see what we know:
On 18A we have 4 initial dies that are coming
>> PTL-H compute tile ~114mm^2
>> PTL-U compute tile
>> CWF 24C tile(is it ~55 mm^2 ?)
>> WCL die (~77-78mm^2 ?)
Intel had confirmed (defect density) D0<0.4 for August 2024. They showed a slide at ITT 2025 without numbering, let's take it as 0.2 or even ~0.15 by Q3 2025.
Take those numbers and calculate Yield for those die sizes with and without considering Parametric Yield(ignore other factors, just rough estimates).

1. From D0 progress w/o parametric Y and other factors
(i) It will never be as low as 10-20%, way more than that.
(ii) no way one is getting 7% absolute increase per month or even anywhere close in any period (for 18A after D0<0.4 to now).

2. Parametric Y and only considering Highest Bins/Top SKUs
(i) Let's say it was around ~25-30% in Q3, even if parametric Y can increase relatively fast it won't be like the net yield reaches ~46-51% in 1 quarter(7% per month). Or if it was for eg. 10-15% at the start of year it won't reach 60-65% within 3-4 Quarters.
Again the comparisons also have to be Apples to Apples, one can't take top bin SKU's net yield a year back and compare it to smallest PTL die(or whole PTL series) at the end of year and claim numbers.

 

[511]

The D0 is very decent it's the parametric being PITA

 

[techjunkie123]

The D0 is very decent it's the parametric being PITA

What's the parametric yield? For someone who doesn't know jack.

Edit: NVM I burned a few trees and figured it out.

 

[OneEng2]

I just read the Tom's article on the Intel "Wafer Supply Problem".

Seems like both Intel and TSMC are having some issues ramping up .... although Intel had projected they would ramp 18A before N2 IIRC.

Still, I wonder about the cost effectiveness of putting a high volume product like Client CPU's on the latest cutting edge (and God awful expensive) node.

With DC you can throw wafers at it and mostly still make the supply (and STILL be profitable). Client? Not so much.

I wonder if this isn't where AMD's architectural strategy of "DC First" might not have some merit?

Intel seems to be going at this backwards IMO. Dropping SMT, Dropping AVX512, etc, just seems like the wrong thing to do ..... if you want to make money that is.

Of course, I could be all completely and utterly wrong.

 

[adroc_thurston]

Seems like both Intel and TSMC are having some issues ramping up .... although Intel had projected they would ramp 18A before N2 IIRC.

Intel problem is that they deprecated a chunk of i7 capacity which they now need.
SPR/EMR are the volume server parts from Intel and boyyyyyyyyyy they have a deficit of i7 goodness now.

I wonder if this isn't where AMD's architectural strategy of "DC First" might not have some merit?

client is getting N2 piles and 2.5D slabs just the same.