Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+4+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[MS_AT]

Intel published updated AVX 10.2 Spec In January supporting only 512 bit vector

To be more precise, it mandates 512b support, but as is today with AVX512(VL) you still get access to 128b and 256b lenghts. But with this change the software will be more uniform what boosts chances of adoption.

 

[511]

To be more precise, it mandates 512b support, but as is today with AVX512(VL) you still get access to 128b and 256b lenghts. But with this change the software will be more uniform what boosts chances of adoption.

I meant that ofc 😅 but it should be backwards compatible with AVX-512

 

[Thunder 57]

Hans DeVries did an article about Intel's "hidden" 64 bit instructions back in the day. It was pretty well known at the time. Sorry your argument is bs, you're the fool and totally worthless fake chump here.

I didn't read the link, so maybe I'm the idiot, though I doubt it.

This has gone way past SIMD now. Can we get back on topic or else make a new thread with regards to who made the first x86 64-bit CPU

I reported this at least a page ago for being completely off topic. The mods must've thought otherwise.

 

[Win2012R2]

cache line 64 bits

CPU cache line is 64 bytes

 

[OneEng2]

It is interesting that core count is increasing so much with little evidence of demand or need for them.

Seems like it would be better to improve ST performance and enhance graphics... Maybe even boost AI engine?

Ah well. The market always wins in the long run.

 

[511]

It is interesting that core count is increasing so much with little evidence of demand or need for them.

Seems like it would be better to improve ST performance and enhance graphics... Maybe even boost AI engine?

Ah well. The market always wins in the long run.

Guess that's there way to take HEDT Market all they have to do Is add 8 more PCI-E Lanes from CPU to 28 and more PCH Lanes add USB 5 Ports directly to CPU all and more memory which is I doubt will go beyond DUAL channel but the speed will get a boost to maybe DDR5 8000.

 

[zir_blazer]

His only article is this one, about a rumour...

Chip Architect: Intel's Prescott Prospects

I remember that article. It was not the only one, you're missing this and this. BTW, the author Hans de Vries is right here, if you want to bring him to the thread.

I began to participate in Hardware forums at late 2003 right before Athlon 64 launch and I remember that whenever Intel was going to adopt AMD64 or roll their own incompatible 64 Bits extensions was one of the bigger topics. Yamhill was the codename for these 64 Bits extensions. It actually wasn't fully AMD64 compatible at first and I recall news report from the era documenting small tweaks that they did from Stepping to Stepping to make it closer to AMD64, like this.
So, that Intel had this Plan B from before Prescott launch was absolutely known, as does the admission of defeat when they began to enable it.

 

[Win2012R2]

It was Andy Grove's company - of course they had Plan B.

 

[511]

It was Andy Grove's company - of course they had Plan B.

he had to retire due to his medical condition IIRC. After Andy the company became worse and after barrette retired it got straight to dumpster fire thanks to the finance bros and MVP being kranzich

 

[Abwx]

I remember that article. It was not the only one, you're missing this and this. BTW, the author Hans de Vries is right here, if you want to bring him to the thread.

I began to participate in Hardware forums at late 2003 right before Athlon 64 launch and I remember that whenever Intel was going to adopt AMD64 or roll their own incompatible 64 Bits extensions was one of the bigger topics. Yamhill was the codename for these 64 Bits extensions. It actually wasn't fully AMD64 compatible at first and I recall news report from the era documenting small tweaks that they did from Stepping to Stepping to make it closer to AMD64, like this.
So, that Intel had this Plan B from before Prescott launch was absolutely known, as does the admission of defeat when they began to enable it.

I linked the oldest article since it was suggested that x64 was present from day one on the P4.

 

[511]

I linked the oldest article since it was suggested that x64 was present from day one on the P4.

There are so many P4 that it is freaking confusing i remember i had one as well can't remember which one was it🤣

 

[zir_blazer]

I linked the oldest article since it was suggested that x64 was present from day one on the P4.

If by P4 we're talking about Prescott, then yes, it was present on die from day one and everyone knew that before launch. The first Pentium 4 Willamatte launch in 2000 predates AMD 2002 x86-64 manuals (Before it was rebranded to AMD64).
Also, a similar situation happened with Willamatte, where Hyper Threading was speculated to exist on die since day one but not enabled:

Originally known under the codename Jackson, Intel announced Hyper-Threading technology which is the marketing spin on SMT. We have hypothesized in the past that what is now known as Hyper-Threading technology has been on all of the Pentium 4 dies created up to this point; it was simply not enabled. Hyper-Threading will finally make its debut next year on the 2-way/4-way Xeon processors and hopefully by the end of the year it will transition down to the desktop level in the Pentium 4.

It was enabled on select Xeon models first (Same with EM64T, a few Xeon models had it enabled before consumer Pentium 4), but no consumer Pentium 4 Willamatte ever got it enabled. It took until the famous Northwood B 3.06 GHz to do so.

Given that Northwood was released in January 2002 and Prescott in early 2004, so Prescott should have been getting designed simultaneously with AMD publication of its 64 Bits extension, I would say that Intel implemented Plan B almost inmediately.

 

[Abwx]

There are so many P4 that it is freaking confusing i remember i had one as well can't remember which one was it🤣

I also got one of the Northwood variant.

If by P4 we're talking about Prescott, then yes, it was present on die from day one and everyone knew that before launch. The first Pentium 4 Willamatte launch in 2000 predates AMD 2002 x86-64 manuals (Before it was rebranded to AMD64).
Also, a similar situation happened with Willamatte, where Hyper Threading was speculated to exist on die since day one but not enabled:



It was enabled on Xeons first (Same with EM64T, a few Xeon models had it enabled before consumer Pentium 4), but no consumer Pentium 4 Willamatte had it enabled. It took until the famous Northwood B 3.06 GHz to do so.

The intel enginer said before the A64 was released, hence my link.
End of the story.

 

[OneEng2]

Guess that's there way to take HEDT Market all they have to do Is add 8 more PCI-E Lanes from CPU to 28 and more PCH Lanes add USB 5 Ports directly to CPU all and more memory which is I doubt will go beyond DUAL channel but the speed will get a boost to maybe DDR5 8000.

Yes, but there really aren't that many HEDT users .... and fewer still that would be willing to pay for the extra work station type architectural enhancements.

I render a few videos a year. My 6 core 5600 does this just fine. Sure, it takes a few minutes, but not so long that it is obnoxious.

If I were rendering video for a living, I wouldn't be using HEDT, I would have a workstation like AMD Threadripper 7000 with 4 or even 8 channel memory. After all, 5-10K for something you make your living on is nothing.

I am just finding it hard to see where all these cores are going to be useful. I am thinking there might have been better things to do with that die area that fill it full of cores that very few people have any need for.

Maybe I am missing something though.

 

[511]

They are using 2 dies instead of 1 large die so I don't think die area is an issue they have much more flexibility this time they can always redirect the dies to single 8+16 sku.

 

[coercitiv]

They are using 2 dies instead of 1 large die so

Dies made where, IFS or TSMC?

 

[511]

Dies made where, IFS or TSMC?

8+16 die is N2 4+8/4+0 is IFS 18AP the Soc die is Intel.
Jaykhin leaked there are P and E core only SKUs as well.

 

[eek2121]

8+16 die is N2 4+8/4+0 is IFS the Soc die is Intel.
Jaykhin leaked there are P and E core only SKUs as well.

From what I understand, the compute tile will be Intel and the tile containing the GPU will be TSMC. They likely are doing this because their GPU stuff has been heavily optimized around using TSMC at this point, and it also allows them to focus on pushing out more compute tile.

Depending on performance characteristics, we will probably see at least some compute tiles made at TSMC. Whether that will be laptop chips or DIY/enthusiast chips, I've no idea.

Side note: I am kind of surprised to see a P4 argument pop up here again after all these years. 🤣

 

[511]

From what I understand, the compute tile will be Intel and the tile containing the GPU will be TSMC. They likely are doing this because their GPU stuff has been heavily optimized around using TSMC at this point, and it also allows them to focus on pushing out more compute tile.

Depending on performance characteristics, we will probably see at least some compute tiles made at TSMC. Whether that will be laptop chips or DIY/enthusiast chips, I've no idea.

The iGPU Tile is 18AP and also they are reusing Intel 3 PTL iGPU Tiles. Intel publicly said more wafer on NVL are Internal vs External considering the shared SoC with desktop Mobile.

Side note: I am kind of surprised to see a P4 argument pop up here again after all these years. 🤣

Yeah I don't even know how it started but all I know is I am part of it 🤣.

 

[OneEng2]

The latest rumor I have heard is that Intel is saying that N2 will be used as well as 18A for Nova Lake. The current explanation is that it is being done for volume reasons and that N2 would likely be used for consumer while 18A would be reserved for DC processors.

Any thoughts on what this may mean for 18A?

 

[LightningZ71]

DC processors typically don't hit as high of peak boost speeds as desktop products. This matches well with rumors that 18A has issues with clocking high efficiently.

 

[511]

The latest rumor I have heard is that Intel is saying that N2 will be used as well as 18A for Nova Lake. The current explanation is that it is being done for volume reasons and that N2 would likely be used for consumer while 18A would be reserved for DC processors.

Any thoughts on what this may mean for 18A?

My expectation on NVL and as for why maybe they are having issue with BSPDN to clock High Ghz due to the heat and thermal challenges and DMR is 18AP.

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[inquiss]

It is interesting that core count is increasing so much with little evidence of demand or need for them.

Seems like it would be better to improve ST performance and enhance graphics... Maybe even boost AI engine?

Ah well. The market always wins in the long run.

Dont be silly, people on this forum will tell you that everyone needs all those cores and that everyone is willing to pay a premium for them.

Honestly, intels high core count nvl feels like not would flop because..who cares about that many cores. 12c 3D vcache will outsell everything next gen. All the high core count stuff doesn't really sell.

 

[alcoholbob]

The high core count is probably a sign Intel is throwing in the towel to actually competing with AMD in IPC during Nova Lake's reign. You don't have to be that efficient either at the higher end of the v/f curve if you have too many cores, since they will all be running at lower clocks. They can just focus on good enough IPC at lower power/clocks.

 

[DrMrLordX]

The latest rumor I have heard is that Intel is saying that N2 will be used as well as 18A for Nova Lake. The current explanation is that it is being done for volume reasons and that N2 would likely be used for consumer while 18A would be reserved for DC processors.

Any thoughts on what this may mean for 18A?

On the one hand, Intel has yet to farm out any of their datacentre CPU production to TSMC, so that's a safe bet based on historical trends; however, we should reserve judgment of what 18a is really capable of doing. It may wind up being another node like Intel 4.