Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[ajsdkflsdjfio]

They might be clever enough but I was referring more to Intel's "excuse" that AVX-512 can't work with E-cores enabled. A hardware/software combination of "trap AVX-512 instruction and context switch over to P-core" could've been done if they hadn't been lazy and so sure of themselves.

If they had been so good, they could've put in the extra effort to keep AVX-512. Haven't heard of Zen4c/5c?

From your words here, one would assume you are talking about Intel e-cores and them not having AVX-512 support.

 

[SiliconFly]

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[igor_kavinski]

AVX-512 for Alderlake and subsequent generations didn't work because of architectural problems

First I'm hearing of that. Did you miss the AT review and other reviews where they TESTED ADL's AVX-512?

The Intel 12th Gen Core i9-12900K Review: Hybrid Performance Brings Hybrid Complexity

www.anandtech.com

Now look how pathetic 13900K is performing without AVX-512:



They could've been a clear 2nd place winner with Raptor AND Arrow.

Guess what all those people with AVX-512 software did? They turned AMD and for the foreseeable future will REMAIN there. That's Intel for you. Ditching their advantage and feeding marketing cores to their "sheep".

 

[SiliconFly]

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[Thunder 57]

Idiot Lisa should have given it a ounce of thought before going all in on AVX-512. Now it's all going to go down the drain.


On Amazon?

Idiot Lisa that has outlasted, what, three Intel CEO's now?

Oh. Thats amazing. Intel should have thought of that.

Do you realize how much latency it introduces?

Clearly Intel did think of it or they never would've wasted die space by including AVX-512.

 

[igor_kavinski]

Do you realize how much latency it introduces?

How about 200ns of latency, switching into Turbo Gear and finishing the entire workload in HALF the time? The latency would've been negligible in the grand scheme.

 

[igor_kavinski]

From your words here, one would assume you are talking about Intel e-cores and them not having AVX-512 support.

You could say both. Intel after Ice Lake behaved like a beginner swimmer trying to navigate murky depths. Just such a sad waste of engineers and their talent.

 

[SiliconFly]

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[ajsdkflsdjfio]

First I'm hearing of that. Did you miss the AT review and other reviews where they TESTED ADL's AVX-512?

You yourself liked this post, which referred to scheduling difficulties surrounding AVX-512 only being available in P-cores and general AVX-512 problems architecturally.

Also It's funny how in those graphs rocket-lake and zen-4 demolish Raptor lake without AVX-512 in those workloads, but in the real world rocket lake is a piece of dogshit under the boot of Alder/Raptor and Zen4 still loses in 90% of applications. Goes to show my point that Intel's decision to cut AVX-512 support did not affect their product's competitiveness at all, not just for intel "sheep" but for consumers in general.

 

[Win2012R2]

How about 200ns of latency

AFAIK faults/traps will take a lot longer than that, been a while since I looked into it though...

Now they're coming out with AVX10 which is not binary compatible with AVX-512. So, good luck to AMD

Any AVX-10 capable CPU will fully support "legacy" AVX-512, so most (of very small number capable of doing it) programmers will just stick with AVX-512

 

[SiliconFly]

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[igor_kavinski]

View attachment 113963
You yourself liked this post, which referred to scheduling difficulties surrounding AVX-512 only being available in P-cores and general AVX-512 problems architecturally.

I liked the part where he stated that it's not realistic to expect E-core to outperform P-core with a few tweaks. That would require a pretty serious redesign.

 

[SiliconFly]

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[igor_kavinski]

An if AVX10 implementation turns out to be good, it clearly shows they're on the right track.

We only find out in 2026, maybe towards the latter half

 

[ajsdkflsdjfio]

I liked the part where he stated that it's not realistic to expect E-core to outperform P-core with a few tweaks. That would require a pretty serious redesign.

Understood and agreed, regardless it's not entirely apparent that AVX-512 implementation didn't have drawbacks in Alder Lake, also Intel disabling it did not affect majority of consumers. It's not a "stupid" decision for Intel themselves and also not a decision that can be put on Pat himself.

 

[Win2012R2]

Ditching the messy AVX-512 in Skymonts is one of the best decisions they've taken. they now have a very clean core. An if AVX10 implementation turns out to be good, it clearly shows they're on the right track.

AVX10 level of support means AVX512 must also be fully supported, with all its "mess".

 

[Kryohi]

Ditching the messy AVX-512 in Skymonts is one of the best decisions they've taken. they now have a very clean core. An if AVX10 implementation turns out to be good, it clearly shows they're on the right track.

Do you seriously think Skymont is good and efficient because it lacks AVX512?

 

[Win2012R2]

Do you seriously think Skymont is good and efficient because it lacks AVX512?

Dropping AVX-512 helped make it a lot smaller for sure

 

[Kryohi]

Dropping AVX-512 helped make it a lot smaller for sure

A bit smaller? Likely yes.
A lot smaller? Nope.
On the list of reasons for Skymont area efficiency, AVX512 is closer to the bottom than to the top. Especially if you take into account the possibility of a "double pumped" implementation ala AMD.

 

[SiliconFly]

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[Win2012R2]

But AVX10 instructions & AVX-512 aren't binary compatible or backward/forward compatible.

They intend to support AVX512 on AVX10 capable processors - "The Intel AVX-512 ISA will be frozen as of the introduction of Intel AVX10 and all CPUID feature flags will continueto be enabled on future P-core processors for legacy support."

Source from Intel - https://cdrdv2-public.intel.com/784343/356368-intel-avx10-tech-paper.pdf

That's the theory, not sure how that will work on AVX10/256 - they will have to use AMD style double pumping to keep AVX512 working (though 256 might mean registers are only 256 bits in the first place, so can't do AMD stylee), this whole AVX10 thing seems to be a big mess that is unlikely to take off anytime soon.

It's going to be 100% dead in the water if AMD says that they won't support it anytime soon, if I was them I'd do just that

A bit smaller? Likely yes.
A lot smaller? Nope.

Intel's AVX512 implementation is hillariously inefficient - we can certainly say that now seeing how good AMD did that in Zen 4 and now 5 - no more excuses - "it's double pumped half speed stuff!" Only thing AMD is missing is 64 byte/cycle from L3 to L2/1, that's definitely a flaw but hopefully fixed in Zen 6.

 

[SiliconFly]

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[Win2012R2]

Things would have worked out differently for AVX-512 (and AMD) if 10nm was on track...

That means, it should take somewhere around ~25% to ~30% of the current Skymont core if included.

It's also likely that power requirements (and thus heat) for this block are such that satisfying them would make whole Skymont design far more difficult - bigger, Skylake had to spend like 50k cycles to "wake up" AVX-512 otherwise even in fat core there were issues with power delivery or somesuch.

 

[ajsdkflsdjfio]

Anyways, it's a ton of work for a edge-case feature on a consumer only product. If they want to add AVX-512 they should add it to Darkmont for server, but it looks like they aren't. AMD is doing the same thing, they didn't add AVX-512 to Zen4/5 to push consumer AVX-512 adoption, they did it to bolster their datacenter products since they use identical architectures pretty much.

 

[DrMrLordX]

Zen4 still loses in 90% of applications.

...wat?

AVX512 may be niche but let's not rewrite history.