Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[igor_kavinski]

at least Pat forced launches on time

He should be nicknamed screwydewy. Other than Lunar Lake's miraculous launch, everything else he launched "on time", was screwed up.

 

[Doug S]

Someone on twitter is saying Pat refused to allow the design and fab split. If true, we should have news of that soon. Before the end of the year.

That was my hot take after seeing the news. If it is true he deserved to be fired sooner. I've been saying Intel needed a clean split for over a year now. They can figure something out to insure the foundry business has the cash to sustain its capital outlays through the end of the decade, then it is on its own. That cash could be treated as up front payments by Intel for foundry output, giving them strong incentive to use that foundry instead of TSMC unless they are totally screwing the pooch.

 

[igor_kavinski]

posted in goodbyte pat thread

 

[RTX]

Agree. Costs ABSOLUTELY matter. Many people here look ONLY at the technology and what Intel/AMD/Others can achieve from a performance standpoint. The only thing that really matters (and Intel is learning this tough lesson the hard way) is if you can make money doing it.

Even if 18A is delivered on schedule, I have doubts that Intel's bottom line will be improving from it. Certainly not in 2025. IMO, Intel is fighting the wrong battle completely. They need to start figuring out how to make a profit .... or someone else will.

... and this is why I am not overly positive about Intel's FINANCIAL prospects even if 18A is a very technically successful process node for them. That equipment is God awful expensive as is each wafer production (due to many more passes needed for GAA, BSPD, and double patterning needed on the 3000 series ASML machines). I agree that Intel needs to get LOTS of external customers for their fab if they are to keep their existing model of business ...... I don't agree that Intel SHOULD keep their existing model .

Current model is fine as is. 18A has the same price/density as their competitor's N3P node with a ppw bonus.

 

[maddie]

Current model is fine as is. 18A has the same price/density as their competitor's N3P node with a ppw bonus.

Honest question. How do you know this?

Also, price for client and cost to produce is not identical.

 

[OneEng2]

Current model is fine as is. 18A has the same price/density as their competitor's N3P node with a ppw bonus.

Based on what information? The honest truth is that we will never know what the internal cost is for Intel to produce 18A wafers, or the price they paid for the EUV equipment and all the NRE to get to 18A (that must be amortized over a number of years to pay it off).

The only clue we will get is when Intel publishes their PRICE per wafer for external customers for 18A. We can then (at a minimum) determine what Intel BELIEVES their cost is with some amount of realism.

What we DO know is that TSMC has drastically raised the price of N2 wafers beyond what N5 class wafers were (including N4). This price has doubled! There are a number of reasons for this that are all well established. GAA requires many more lithography steps than FinFET. BSPDN requires even more steps than just GAA.

Every step involves failure % that lowers yields.

In other words, there is NO WAY on God's green earth that 18A has the same price per wafer as N3P. It will be significantly more expensive.

 

[SiliconFly]

.

 

[Josh128]

Someone on twitter is saying Pat refused to allow the design and fab split. If true, we should have news of that soon. Before the end of the year.

Its quite obvious even to an outsider that this is almost certainly the case. Pats vision as CEO was to save the Intel that he always knew, fab+design. Obviously his 5N/4Y plan to regain node leadership parity was needed to make that happen. Because it probably was not going to be on schedule, they pushed him out. 100% certain fabs will be spun off at this point.

Retired Engineer from Twitter posted the below:

The (only?) way forward?

Spin-off manufacturing to a consortium comprising the most consequential customers like Apple, Nvidia, AMD, Qualcomm, Broadcom, Microsoft, Amazon, Google, etc., further backed by USG.

Use proceeds to rebuild Product group as fabless company.

— RetiredEngineer® (@chiakokhua) December 3, 2024

And I believe he is 100% correct in this assessment.

 

[dttprofessor]

Its quite obvious even to an outsider that this is almost certainly the case. Pats vision as CEO was to save the Intel that he always knew, fab+design. Obviously his 5N/4Y plan to regain node leadership parity was needed to make that happen. Because it probably was not going to be on schedule, they pushed him out. 100% certain fabs will be spun off at this point.

Retired Engineer from Twitter posted the below:



And I believe he is 100% correct in this assessment.

It's the worst plan for intel.

 

[Josh128]

It's the worst plan for intel.

Its the only viable option now.

 

[igor_kavinski]

Intel wouldn't be in this situation if after their experience with 10nm troubles, they had simply gone fabless and left the foundry part to fend for itself. Both their design and fab sides lived off of each other which allowed them to mask internal issues for a decade or more. Krzanich being from the fab side let the design side rot and even didn't care that much about the fab side because he didn't have the vision to foresee a world where AMD and TSMC steamrolled over Intel. And no one could've imagined Apple and Qualcomm joining the foray to further humiliate Intel.

The Covid era gave them a false sense of security where they thought they would keep selling laptops for years yet even 11th gen laptops can still be found in online stores and selling with upgraded 32GB RAM to make them look more attractive to newer options. It seems retailers were able to sell off their AMD Zen laptops much quicker. The single dumbest thing Intel did was their hybrid core strategy. A 10 core Lion Cove with large L3 or even a slightly slower L4 and a 16 core Skymont, both monolithic and both on Intel 7, could have lived side by side and customers would've chosen whichever they deemed enough for their needs.

 

[GTracing]

Intel wouldn't be in this situation if after their experience with 10nm troubles, they had simply gone fabless and left the foundry part to fend for itself.

From what I've heard, there wasn't enough capacity at TSMC and Samsung in 2018 for Intel to go fabless.

 

[OneEng2]

Very true. But from what they said, 18A costs less than N2.

And Intel having it's own foundry gives them an edge. They can customize it to their heart's content and most importantly, don't have to dole out billions every year to TSMC.

18A may cost "Them" less than N2 depending on how they calculate "costs them". I am absolutely positive (I have plenty of C-Suite experience in companies) at this point that the numbers within Intel's own financial calculations are .... creative in nature .

Intel having its own foundry only gives them an edge with respect to how well that process works with their design. Having their own proprietary 18A process on a leading edge node using leading edge technology (GAA and BSPDN) is God awful expensive..... that they absolutely "dole out billions every year" for.

I think that this is the core of issue that Pat G's direction caused. Even if it "worked well", it is so expensive that you can't make money doing it.

 

[jur]

BSPDN reduces the number of metal layers and also relaxes pitches. Once the foundry knows how to do it well, it probably even reduces cost of the process. Of course development and getting everything to work is expensive. That said, 18A supposedly has 21nm M0, which is still very close to the limit for EUV double patterning. Intel is targeting very high with this process. TSMC 2N can't be much denser, because it's impossible with current tech. They would need high NA EUV or multiple (not just double) low NA patterning. I suspect that N2 is denser mainly because it has high density libraries. Fyi, N3B supposedly has 23nm M0, so it's less dense in theory.

Intel having its own foundry only gives them an edge with respect to how well that process works with their design. Having their own proprietary 18A process on a leading edge node using leading edge technology (GAA and BSPDN) is God awful expensive..... that they absolutely "dole out billions every year" for.

I think that this is the core of issue that Pat G's direction caused. Even if it "worked well", it is so expensive that you can't make money doing it.

The whole point of foundry is that external customers would use processes - that's how they get their ROI. Getting external customers is hard and slow, but once they get a few successfully on board. Imo having foundry means that you develop process for customers not just for your design and seems like they were doing that with 18A-P.

 

[igor_kavinski]

From what I've heard, there wasn't enough capacity at TSMC and Samsung in 2018 for Intel to go fabless.

This is their biggest problem. For them, it's either go big or don't bother. They could've started experimenting with test samples. Maybe sold a batch of a million limited edition TSMC fabbed CPUs to some OEM to gain experience. This is essentially what they did with their discrete GPU designs but for CPU, they were just too proud and arrogant to try something new.

 

[SiliconFly]

.

 

[Meteor Late]

Intel wouldn't be in this situation if after their experience with 10nm troubles, they had simply gone fabless and left the foundry part to fend for itself. Both their design and fab sides lived off of each other which allowed them to mask internal issues for a decade or more. Krzanich being from the fab side let the design side rot and even didn't care that much about the fab side because he didn't have the vision to foresee a world where AMD and TSMC steamrolled over Intel. And no one could've imagined Apple and Qualcomm joining the foray to further humiliate Intel.

The Covid era gave them a false sense of security where they thought they would keep selling laptops for years yet even 11th gen laptops can still be found in online stores and selling with upgraded 32GB RAM to make them look more attractive to newer options. It seems retailers were able to sell off their AMD Zen laptops much quicker. The single dumbest thing Intel did was their hybrid core strategy. A 10 core Lion Cove with large L3 or even a slightly slower L4 and a 16 core Skymont, both monolithic and both on Intel 7, could have lived side by side and customers would've chosen whichever they deemed enough for their needs.

The reason for this strategy was to compete against AMD's high core count SKUs

 

[Doug S]

Intel wouldn't be in this situation if after their experience with 10nm troubles, they had simply gone fabless and left the foundry part to fend for itself.

If they "left it to fend for itself" it would have gone under immediately. It was not a real foundry in meaningful any way. Still requiring use of Intel proprietary tooling for design work would have made it difficult to use for customers. Plus offering its services after all the well publicized 10nm issues would be exactly the wrong time to try to win customers. The foundry needed investment to build fabs for the EUV age, and equip them, and that money had to come from somewhere. It wouldn't be forthcoming if Intel "left the foundry part to fend for itself".

They can't even do that today, when they split Intel needs to leave behind a big pile of cash for it so it can execute on its fab building plans in Ohio. Without follow through on that, no matter how good 18A and future processes are they won't be able to win much business, because they won't have much capacity. But at least it is better shape as far as being a real foundry, since Intel has abandoned its proprietary stuff for industry standards.

 

[igor_kavinski]

The reason for this strategy was to compete against AMD's high core count SKUs

Why compete when they can do their own thing? Their mistake was trying to imitate AMD's approach when AMD was only listening to its customers and giving them what they wanted. Intel should have LISTENED to their own customers.

 

[RTX]

BSPDN reduces the number of metal layers and also relaxes pitches. Once the foundry knows how to do it well, it probably even reduces cost of the process. Of course development and getting everything to work is expensive. That said, 18A supposedly has 21nm M0, which is still very close to the limit for EUV double patterning. Intel is targeting very high with this process. TSMC 2N can't be much denser, because it's impossible with current tech. They would need high NA EUV or multiple (not just double) low NA patterning. I suspect that N2 is denser mainly because it has high density libraries. Fyi, N3B supposedly has 23nm M0, so it's less dense in theory.

The whole point of foundry is that external customers would use processes - that's how they get their ROI. Getting external customers is hard and slow, but once they get a few successfully on board. Imo having foundry means that you develop process for customers not just for your design and seems like they were doing that with 18A-P.

That guy said it was for another process after 18A/variants.

 

[coercitiv]

C&C analysis for ARL:

Examining Intel's Arrow Lake, at the System Level

Arrow Lake is the codename for Intel's newest generation of high performance desktop CPUs.

chipsandcheese.com

Some tidbits about cache performance:

Unfortunately, a longer ring bus and higher L3 capacity translate to higher latency. L3 load-to-use latency on Arrow Lake is north of 80 cycles from a P-Core, compared to about 52 cycles on Lunar Lake. The cycle count penalty is high enough that Arrow Lake’s actual L3 latency is higher than Lunar Lake’s, even though Arrow Lake runs at higher clocks.

Overall, Arrow Lake largely carries forward the caching strategy used in prior generations. Raptor Lake and Alder Lake before had lackluster L3 performance, but compensated with larger L2 caches than their AMD counterparts. Intel also has larger cores that can speculate further ahead of a stalled instruction, putting them in a better spot to maintain decent throughput in the face of long load latency. AMD isn’t too different in that regard. Zen 4 doubled L2 capacity to 1 MB, significantly reducing average L3 traffic in the process. Recent Arm server chips also use large (1 or 2 MB) L2 caches to mitigate L3 latency. Thus other CPU makers are also taking advantage of process node improvements to keep more data closer to their cores. Arrow Lake does lean a bit harder on L2 capacity than other architectures, because it needs to deliver high per-core performance while using a relatively slower L3.

 

[511]

18A may cost "Them" less than N2 depending on how they calculate "costs them". I am absolutely positive (I have plenty of C-Suite experience in companies) at this point that the numbers within Intel's own financial calculations are .... creative in nature .

For Intel that cost is always going to be less than paying TSMC for 18A even vs N3 lol
An Example let N3 cost 19K (50% margin for tsmc included) from TSMC but 18A cost like 22-23K(35-40% margin) 25K for N2 ( I wil not believe 30K it is ridiculous price a 25-30% price increase seems likely vs N3) .
The thing is they are paying margin to themselves it's like making an item for 100 and asking 140 for it and paying 140 to yourself
Sidenote TSMC N3 wafer price 19-20K N2 interpolated by increasing it by 25-30% 18A calculated based on Intel slide of cost between N3/N2

Intel having its own foundry only gives them an edge with respect to how well that process works with their design. Having their own proprietary 18A process on a leading edge node using leading edge technology (GAA and BSPDN) is God awful expensive..... that they absolutely "dole out billions every year" for.

I think that this is the core of issue that Pat G's direction caused. Even if it "worked well", it is so expensive that you can't make money doing it.

You can't make money in short terms with all the issues the foundry had now the foundry is improving but the products have a problem cough cough ARL RPL MTL LNL

 

[Det0x]

Intel is starting to become the "It's coming!" machine.

Intel announces Arrow Lake fix coming within a month — Robert Hallock confirms poor gaming performance is due to optimization issues

A fix is on the way.

www.tomshardware.com

Great, only a few more days until we get the fix for Arrow Lakes poor gaming performance!

.. Because intel can be trusted, right guys ? 🤣

 

[sgs_x86]

Great, only a few more days until we get the fix for Arrow Lakes poor gaming performance!

.. Because intel can be trusted, right guys ? 🤣

I do not think they can improve the latencies with microcode or bios updates. I hope I am wrong, but I do not think gaming perf will increase by more than 5-10%.

 

[OneEng2]

For Intel that cost is always going to be less than paying TSMC for 18A even vs N3 lol

Is it really?

18A development is estimated at around 10bn USD. That is just NRE.

Having a fabrication plant? Having headcount to run the plant? Materials to run and maintain the plant? Management to run the plant? etc, etc, etc.

AMD (and many others) are making very good money without a fab of their own (and without paying for all that overhead). Intel still has ~70% of the market and has ASP's about equal to AMD's. Why isn't Intel's profit 3x that of AMD (since they sell 3x more product)?

In a board meeting, the proof is in the pudding. You either make the numbers, or you don't. It is quite difficult to make an argument that your ideas "worked" because it was a technical success..... or that you are paying less per wafer doing it your way.... or that you are gaining market share. If you aren't making a profit (and in specific if your competitor that sells 3x less than you IS making a profit) you are in trouble.

You would think that the "gaining market share" would get you something, but the answer is just that selling more at a LOSS is just losing more, so who cares?

As I have said, Intel's problems will not be fixed even if 18A works very well. They have got to become much more lean and efficient than they are now in order to make money.