Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Hulk]

It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

 

[511]

It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

The performance regression is due to L3 and mix of other Factors LNC is not a big upgrade either it's just Meh.
If it was same performance at half the power without regression it would have been good but it is a mixed bag a 3-5% gaming regression would have been swallowable with these uplift I don't see U9 285K as a good value outside overclockers and Platform Features like tons of NVMe and IO

 

[reaperrr3]

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression.

Zen5 was a ground-up redesign of the pipeline, lost some of Zen4's optimizations, focused more on DC workloads than desktop, is still 4-wide per decoder/thread, and rumored to have gone through multiple design team switches and a generally hiccup-ridden development.

Also, most significant IPC increases in the past for games came alongside significant cache size/topology bumps (Zen2: doubled L3 per core, Zen3: doubled cores per CCX->up to 2x L3 per core/thread, Zen4: doubled L2, ADL: massive cache bump over CFL/ICL), of which Zen5 has virtually none.

And LNC in ARL looks like either their chiplet technology is still inferior to AMD's and holding back the cores, or they just borked the core's design somewhere. Not sure you should take ARL as example for IPC headroom petering out.

 

[mikk]

Maybe we can expect a 5% bump from Darkmont over Skymont, there are some changes.

https://twitter.com/x/status/1852244184696021423

https://twitter.com/x/status/1852285701951307808

The E core team can do this with some tweaks here and there (like Crestmont). The Cove team usually needs big changes for the same performance increase. We don't know about Cougar Cove though. Maybe they can fix some things over Lion Cove.

 

[Hulk]

Zen5 was a ground-up redesign of the pipeline, lost some of Zen4's optimizations, focused more on DC workloads than desktop, is still 4-wide per decoder/thread, and rumored to have gone through multiple design team switches and a generally hiccup-ridden development.

Also, most significant IPC increases in the past for games came alongside significant cache size/topology bumps (Zen2: doubled L3 per core, Zen3: doubled cores per CCX->up to 2x L3 per core/thread, Zen4: doubled L2, ADL: massive cache bump over CFL/ICL), of which Zen5 has virtually none.

And LNC in ARL looks like either their chiplet technology is still inferior to AMD's and holding back the cores, or they just borked the core's design somewhere. Not sure you should take ARL as example for IPC headroom petering out.

Okay. What is the IPC gain overall for LNC and Zen 5?

 

[511]

Maybe we can expect a 5% bump from Darkmont over Skymont, there are some changes.

https://twitter.com/x/status/1852244184696021423

https://twitter.com/x/status/1852285701951307808

The E core team can do this with some tweaks here and there (like Crestmont). The Cove team usually needs big changes for the same performance increase. We don't know about Cougar Cove though. Maybe they can fix some things over Lion Cove.

You know his tweets are protected lol but those are major changes
Instructions decode 20B-> 24B increase in per cycle bandwidth
Two Taken Conditional branch
L2 cache improvement
It will be a Gracemont -> Crestmont Jump 3-7% IPC considering the small core is RPC IPC so higher IPC than a 5th gen Xeon core outside of AVX-512 🤣 and consuming way less power i hope Clearwater Forest is actually good with these

 

[DavidC1]

Just to be sure, is 20% speculation from you or was something like that said by Intel or new reports?

How would someone be able to speculate that accurately by a simple comment by Broadcom that 18A is terrible?

By Reuters or Bloomberg. It's a recent report. It's in the Intel Q3 thread.

But it's just dLDOs.

It's how they used it that was unique.

 

[Kepler_L2]

It is getting hard for me to take Intel process timelines seriously because they seem to miss their deadlines so regularly. ARL disappoints architecturally and isn't on Intel 20A. Might be time for an AMD/Intel pair trade.

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Without software help like new instructions or something I don't see how we get another 15 to 20% increase on a generation from either Zen 5 or LNC? 8 wide is already too wide, right?

On that same note, considering performance regression is LNC still +9% over Raptor Cove?

Zen5 is still much smaller vs Apple cores.

4-wide decode vs 10-wide
8-wide rename vs 10-wide
6 ALU vs 8 ALU
448 ROB vs 960

 

[Hitman928]

Okay. What is the IPC gain overall for LNC and Zen 5?

From the SPECint numbers we have, around 10% for Zen 5 and low single digits for LNC.

 

[511]

Zen5 is still much smaller vs Apple cores.

4-wide decode vs 10-wide

2*4 Decode 🙂

 

[511]

Maybe Nova is still in planning phase if they need to launch by H2 2026 they can tape out A0 within 12 -18 months so Q1-Q2 25

 

[DavidC1]

It just seems like IPC-wise x86 is nearly topped out. Zen 5 didn't show big gains and Lion Cove showed gains and regression. It seems more likely that the E cores will approach current ST iso frequency performance and peter out as well at that performance level as well, they just end up at that performance level in a more area efficient manner.

Or, there's a lot to go and they haven't found a way yet. Don't think it's just conjecture people are saying BOTH of the x86 vendors suck in execution.

2*4 Decode 🙂

Only when SMT is active.

That in itself is not significant though. Maybe 5% at best for average.

 

[Kepler_L2]

2*4 Decode 🙂

For 1T is just 4-wide.

 

[511]

Or, there's a lot to go and they haven't found a way yet. Don't think it's just conjecture people are saying BOTH of the x86 vendors suck in execution.

Only when SMT is active.

That in itself is not significant though. Maybe 5% at best for average.

These results says something else

https://twitter.com/x/status/1845436706025021930

 

[511]

Also found these while searching

 

[cannedlake240]

You know his tweets are protected lol but those are major changes
Instructions decode 20B-> 24B increase in per cycle bandwidth
Two Taken Conditional branch
L2 cache improvement
It will be a Gracemont -> Crestmont Jump 3-7% IPC considering the small core is RPC IPC so higher IPC than a 5th gen Xeon core outside of AVX-512 🤣 and consuming way less power i hope Clearwater Forest is actually good with these

That seems like too many changes for what's essentially a node shrink tick core. Also wonder if the NVL e core naming change has actual meaning... It could signal a major Zen 5 like redesign for the uarch, which then can be iterated on to take the place of the current P core

 

[igor_kavinski]

Non-English YT video showing the 245K as more efficient and faster than 9600X:

But slower in games obviously.

No idea how accurate or true the bit about lower power consumption is, though.

Maybe Intel has a chance now to convince budget users to go for Arrow Lake?

EDIT: Scratch that! From same video:



Left ARL and right Zen 5 in PUBG. ARL is legendarily bad!



Guy trying his best to teach his followers that Zen 5 delivers more frames using more power

 

[DAPUNISHER]

20 review geomean

 

[Hitman928]

No idea how accurate or true the bit about lower power consumption is, though.

Seems to not be true:

 

[511]

20 review geomean

View attachment 110776

While not mentioning power at all and Price
> 285k Nothing good about it
> 265K okay price and App performance if someone is buying Intel and does not care much about gaming it is the CPU to buy
> 245K would be fine if it was like 280$

 

[igor_kavinski]

> 285k Nothing good about it

Maybe they can release a 280K SKU with 6P+16E to dial down the power consumption a bit or higher all core clocks for both P and E cores (maybe 290K in that case?).

 

[GTracing]

These results says something else

Zen5 can execute 8 instructions per cycle. It can't decode more than 4 per cycle on a single thread.

Here's where chips and cheese discusses it in their Strix Point article.

Zen 5 can sustain higher instruction throughput than Intel Meteor Lake’s Redwood Cove P-Cores, but only for small instruction footprints or when both SMT threads are loaded. If only a single SMT thread is active, Intel’s larger 64 KB instruction cache and conventional 6-wide decoder can hand it a lead when code spills out of the micro-op cache.

Plenty of other cores can execute more instructions than they can decode, Zen4 for example.

AMD’s Strix Point: Zen 5 Hits Mobile

AMD’s Zen line has gone a long way since it brought AMD’s CPU efforts back from the dead.

chipsandcheese.com

 

[SiliconFly]

.

 

[MS_AT]

Zen5 can sustain 8 ops from uop cache, but they have to be a mix of int / simd / mem. Games are more problematic bc for them uop cache is less effective. [up to 80 % hit rate for zen4 when zen 5 enjoys over 90% hit rate across spec int according to C&C]. That is to say 4wide decode doesn't seem to be immediate issue for Zen5.

 

[dttprofessor]

6P+16E/4P+16E non k should be a good choice.