Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Doug S]

My theory is it is scheduling on the wrong core type. And maybe also not clocking appropriately...

I don't have a dog in this fight since I don't care about gaming performance but it is funny how everyone is dismissing it and didn't learn the lesson they learned with Zen 5, which had a pretty rough rollout that required a firmware update (maybe more than one I don't follow this stuff as closely you all do) post launch to reach its "real" performance. So maybe Arrow Lake will need that and/or some Intel updates to address Windows scheduling behavior.

 

[igor_kavinski]

So maybe Arrow Lake will need that and/or some Intel updates to address Windows scheduling behavior.

So gaming hardware is now going to adopt the game post-launch mega patch/fixes model...

 

[Joe NYC]

Basically Admitting the design was wrong and CPU+IMC should have been in the same tile

Not necessarily wrong design. AMD has been dealing with this challenge (successfully) since the dawn of the chiplets. Maybe a skill issue.

BTW, my understanding is that Foveros should have better latency than SerDes on AMD chips, so the latency penalty for Arrow Lake should still be lower than latency penalty on Zen chips.

 

[Joe NYC]

You're not gonna believe what PTL is doing

I thought PTL has the same basic tile set up. Is that correct, or is Intel making some changes?

 

[coercitiv]

Not necessarily wrong design. AMD has been dealing with this challenge (successfully) since the dawn of the chiplets. Maybe a skill issue.

IMHO it a sub-optimal design. AMD keeps the MC on the IOD because they need to scale in terms of core count. Intel has no such requirement. I would understand this type of split if ARL was able to scale to multiple compute tiles.

 

[igor_kavinski]

I would understand this type of split if ARL was able to scale to multiple compute tiles.

Maybe at some point THAT was the plan but they deemed it too costly. The groundwork had already been laid so now they have to eat their veggies.

Remember the rumored 40 core Beast Lake?

Looking forward to Demon Lake now

 

[511]

Not necessarily wrong design. AMD has been dealing with this challenge (successfully) since the dawn of the chiplets. Maybe a skill issue.

BTW, my understanding is that Foveros should have better latency than SerDes on AMD chips, so the latency penalty for Arrow Lake should still be lower than latency penalty on Zen chips.

It's not foveros fault but the Fabric/Ring

 

[511]

Maybe at some point THAT was the plan but they deemed it too costly. The groundwork had already been laid so now they have to eat their veggies.

Remember the rumored 40 core Beast Lake?

Looking forward to Demon Lake now

You mean Demo Lake

 

[adroc_thurston]

or is Intel making some changes?

SOC and compute tiles are one now.

 

[SolidQ]

GN video

 

[Joe NYC]

IMHO it a sub-optimal design. AMD keeps the MC on the IOD because they need to scale in terms of core count. Intel has no such requirement. I would understand this type of split if ARL was able to scale to multiple compute tiles.

There are other issues that could favor splitting compute from SOC, such as using appropriate / optiprocess node. And for Intel, to be able to move back to its own fabs tile by tile.

BTW, one of the reason to use more expensive Foveros packaging (rather than organic) was ability to use essentially a parallel connection rather than serial, with benefit of having better bandwidth, better latency, lower power overhead. Where did those benefits go?

 

[Abwx]

Maybe at some point THAT was the plan but they deemed it too costly. The groundwork had already been laid so now they have to eat their veggies.

Remember the rumored 40 core Beast Lake?

Looking forward to Demon Lake now

Those names wont happen, Gelsinger being a supersticious devout he would be afraid to be damned, lol.

 

[alcoholbob]

Reviewer forgot to use APO?

I thought APO was built-in to the system now with 200 series?…

 

[511]

Those names wont happen, Gelsinger being a supersticious devout he would be afraid to be damned, lol.

Blame all you want on him at least he fixed many issues that none of the past 2 CEOs were able to fix he simply took a cautious approach of cutting project that may or may not bear fruit Intels P Core team was being carried by their Fabs now that is gone they are seeing the results and he knows it that is why he is so insistent on fabs the fabs carried Intel hard.

 

[poke01]

https://twitter.com/x/status/1849069441335566558

Let’s see if Intel improves this in the next six months.

 

[igor_kavinski]

I thought APO was built-in to the system now with 200 series?…

It's a utility that needs to be downloaded from Microsoft Store AFAIK.

EDIT: https://apps.microsoft.com/detail/9nz98vnk5x1s?hl=en-us&gl=US

 

[gdansk]

https://twitter.com/x/status/1849069441335566558

Let’s see if Intel improves this in the next six months.

Isn't balanced the default in Windows?
That should be the profile that Intel doesn't want to suck lol

 

[Saylick]

https://twitter.com/x/status/1849069441335566558

Let’s see if Intel improves this in the next six months.

*sigh* This meme I've created gets more and more relevant with each passing day.
'

 

[cannedlake240]

WIll they even get to that point? This ARL firmware fiasco (if it really even IS that) is going to wreak what's left of their stock price!

A tiniest hint from Jensen about using Intel Fabs for rtx6050 and stock market will pretend Intel never really needed desktop

 

[Joe NYC]

I hope this is not true. Stay away from ropes!

https://twitter.com/x/status/1849114093333963130

 

[cannedlake240]

Not necessarily wrong design. AMD has been dealing with this challenge (successfully) since the dawn of the chiplets. Maybe a skill issue.

They have the blazing fast L3 cache though. Intel's 192K L1.5 and large L2 don't seem to make up for slow L3 and now main memory

 

[Kocicak]

OC3D RAM testing:





Can any of these results explain poor gaming performance? Latency is quite similar between the CPUs and Arrow lake CPUs seem to have very quick read speeds.

 

[gaav87]

Link to OC3D article cached if anyone interested:

Intel Core Ultra 285K, 265K, and 245K CPU Review

Intel has fixed some BIG problems, but at what cost?

cc.bingj.com

 

[GTracing]

GN video

Interesting to see some of his testing tools.

Steve is heavily implying that Arrow Lake uses more power from the motherboard connector and he hints that the power consumption figures in Intel's marketing materials don't take into account.

 

[Kocicak]

Link to OC3D article cached if anyone interested:

Intel Core Ultra 285K, 265K, and 245K CPU Review

Intel has fixed some BIG problems, but at what cost?

cc.bingj.com

Well, it contains just the first page of the review.