Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Ghostsonplanets]

Nah, it's still 8 Xe Cores, the documents literally show that. But one Xe Core has only 8 EUs in Battlemage, but these EUs have double the Width. So Lunar Lake still has 8 Raytracing Units etc. because these are matched with Xe Cores.

Thanks! I'll update my post correctly then.

 

[mikk]

https://twitter.com/x/status/1780556976839376904

View attachment 97147

None of these are news, but sharing anyway.

Memory power is included in the TDP, that was new to me. That's why they are using odd numbers like 17W or 30W.

 

[coercitiv]

Including the memory power while bumping the ratings accordingly seems like a reasonable approach.

 

[SiliconFly]

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[Thibsie]

I mean I think it'd be both lower effort to develop and much easier to run to just have an app with that information and a regular search bar on your mobile phone. And cheaper to the store as well, they don't have to fit a computer to the end of every aisle.

But it's AI, man !

 

[Gzxy]

... You're aware this is incredibly optimistic, right? Intel has been doing big changes in the past 5 years and that amounted for two jumps of 19%. And the early leaks around ARL show it barely being faster than RPL...

MTL-U is still a good SoC for the average consumer and Intel can offer it at cheaper prices with good availability. The move to Intel 3 will also offer a 10% bump in energy efficiency.

Also, everything Arrow Lake will be based on Meteor Lake. It reuses the same tiles, with an updated tGPU tile to include XMX and the new Compute Tile.

LNC being barely faster that RPL were projections probably based on really old 20A targets. Obviously most stuff we are talking here are rumors and assumptions. Think about it.
Golden Cove (2021)
Raptor Cove = Golden Cove+
Redwood Cove = ~Raptor Cove
Lion Cove = Raptor Cove+ (2024-2025)

That's bullshit. 4 years the same arch for P cores?

Also if Lion Cove is so weak that LNL will end up bad, it wont be able to even beat X Elite in ST.

Then moving to desktop. 14th Gen is basically 13th Gen with DLVR and crazier clocks. X3D crashes them at gaming. Zen 5 will have V-cache. ARL will have clock regressions compared to 14th Gen which means if we are talking about a ~5% IPC over RPL, i dont see it beating even 14th Gen in gaming.

Finally Intel7 -> Intel4-> TSM N3B and 20A.
Intel4 was a risky node, they didn't really believe it would come out good when they decided about the arch of MTL so i suppose they wanted their CPU tile to be as small as possible to not have huge yield issues.

 

[S'renne]

LNC being barely faster that RPL were projections probably based on really old 20A targets. Obviously most stuff we are talking here are rumors and assumptions. Think about it.
Golden Cove (2021)
Raptor Cove = Golden Cove+
Redwood Cove = ~Raptor Cove
Lion Cove = Raptor Cove+ (2024-2025)

That's bullshit. 4 years the same arch for P cores?

Also if Lion Cove is so weak that LNL will end up bad, it wont be able to even beat X Elite in ST.

Then moving to desktop. 14th Gen is basically 13th Gen with DLVR and crazier clocks. X3D crashes them at gaming. Zen 5 will have V-cache. ARL will have clock regressions compared to 14th Gen which means if we are talking about a ~5% IPC over RPL, i dont see it beating even 14th Gen in gaming.

Finally Intel7 -> Intel4-> TSM N3B and 20A.
Intel4 was a risky node, they didn't really believe it would come out good when they decided about the arch of MTL so i suppose they wanted their CPU tile to be as small as possible to not have huge yield issues.

I like how they are so ready to jump on the Zen 5 hype train but not skeptical of the literal earliest leaks on ARL based on a slide that has minimal context.

It didnt even have any details on what config is used for the testing nor what stepping stage it was at etc...

Oh wait its great to be biased atm apparently

 

[reggie_fils_aime]

I like how they are so ready to jump on the Zen 5 hype train but not skeptical of the literal earliest leaks on ARL based on a slide that has minimal context.

It didnt even have any details on what config is used for the testing nor what stepping stage it was at etc...

Oh wait its great to be biased atm apparently

This might have something to do with recently observed reality vis-a-vis intel puts out things late and they tend to be underwhelming/AMD under promises, over delivers, and does it on time. People tend to value "what have you done for me lately"!

 

[Geddagod]

LNC being barely faster that RPL were projections probably based on really old 20A targets.

Igor's leak was pretty new, and by then the rumors that the desktop i9 sku won't be 20A had been around for a while.

That's bullshit. 4 years the same arch for P cores?

It's not the same arch. Big changes, just lower IPC gains than expected. What is the expectation now? ~15%? With a small frequency regression vs RPL? That's not unreasonable at all.

i dont see it beating even 14th Gen in gaming.

Depends on how the mem fabric can scale to higher power, apparently.

I like how they are so ready to jump on the Zen 5 hype train but not skeptical of the literal earliest leaks on ARL based on a slide that has minimal context

Plenty of people doubt the Zen 5 hype train. I'm just not on this website that much cuz half the time it literally doesn't even load in for some reason lmao

It didnt even have any details on what config is used for the testing nor what stepping stage it was at etc...

It's a performance projection. Companies release performance projections for final performance months or even years before launch. Remember the ~2x performance gain from GNR leak from some old documents a couple years ago? Do you think that was ES silicon getting those scores? Intel themselves on their RPL development timeline slide showed how they release early performance projections before they even power on the silicon, they don't have to be testing ES samples to get those.

 

[AMDK11]

LNC being barely faster that RPL were projections probably based on really old 20A targets. Obviously most stuff we are talking here are rumors and assumptions. Think about it.
Golden Cove (2021)
Raptor Cove = Golden Cove+
Redwood Cove = ~Raptor Cove
Lion Cove = Raptor Cove+ (2024-2025)

That's bullshit. 4 years the same arch for P cores?

Also if Lion Cove is so weak that LNL will end up bad, it wont be able to even beat X Elite in ST.

Then moving to desktop. 14th Gen is basically 13th Gen with DLVR and crazier clocks. X3D crashes them at gaming. Zen 5 will have V-cache. ARL will have clock regressions compared to 14th Gen which means if we are talking about a ~5% IPC over RPL, i dont see it beating even 14th Gen in gaming.

Finally Intel7 -> Intel4-> TSM N3B and 20A.
Intel4 was a risky node, they didn't really believe it would come out good when they decided about the arch of MTL so i suppose they wanted their CPU tile to be as small as possible to not have huge yield issues.

GoldenCove
RaptorCove (GoldenCove with larger L2)
RedwoodCove (GoldenCove+)

RedwoodCove is not RaptorCove as there are changes to the core itself, but they are quite cosmetic. The most noticeable change is the move from L1-I 32 KB in the 8-way to 64 KB in the 16-way. The last time Intel changed L1-I from 16KB 4-way in Pentium III to 32KB 8-way in Banias was over 20 years ago. As far as I know, LionCove inherits L1-I 64KB 16-way + already existing L1-D 48KB 12-way from SunnyCove/CypressCove.

LionCove is a new core, just like SunnyCove and then GoldenCove compared to Skylake.

Besides, I don't know what you base your conclusions on. We don't know how high LionCove's IPC is. It may be, for example, 20-25%, but the clock speed is much lower. Not enough data.

From leaks and some of my guesses, LionCove has an 8-way instruction decoder(GoldenCove 6-Way), ROB entries 750-800(GoldenCove 512), and may have 6-7x ALU(GoldenCove 5x ALU), 7x AGU(4x Load + 3x Store)(GoldenCove 5x AGU(3x Load + 2x Store)), SMT4 (disabled in ArrowLake?) mainly for Xeon needs and a full 2x 512bit/4x 256bit FPU.

 

[Doug S]

Or the last time I went to get a 8/3 AWG wire stripper.

Unless you're stripping a lot of it what's wrong with using a razor knife to strip the insulation?

 

[SiliconFly]

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[Gzxy]

GoldenCove
RaptorCove (GoldenCove with larger L2)
RedwoodCove (GoldenCove+)

RedwoodCove is not RaptorCove as there are changes to the core itself, but they are quite cosmetic. The most noticeable change is the move from L1-I 32 KB in the 8-way to 64 KB in the 16-way.

LionCove is a new core, just like SunnyCove and then GoldenCove compared to Skylake.

Besides, I don't know what you base your conclusions on. We don't know how high LionCove's IPC is. It may be, for example, 20-25%, but the clock speed is much lower. Not enough data.

From leaks and some of my guesses, LionCove has an 8-way instruction decoder(GoldenCove 6-Way), ROB entries 750-800(GoldenCove 512), and may have 6-7x ALU(GoldenCove 5x ALU), 7x AGU(4x Load + 3x Store)(GoldenCove 5x AGU(3x Load + 2x Store)), SMT4 (disabled in ArrowLake?) mainly for Xeon needs and a full 2x 512bit FPU.

1) Not a comp arch guy but small changes from Golden -> Redwood could be stuff associated with newer Ram or with the Layout. Alder L and Raptor L were monolithic designs and MTL is Tile based.

2) Depending your node's capabilities, your time and the capital that you allocate you can set different IPC targets. Raptor Lake was not an expensive arch to design. Meteor Lake was expensive in terms of designing and manufacturing because they moved from monolithic arch to tiles and packaging.

3) We don't know how far the clocks can be pushed for 3NB. Zen 4 pushed the clocks really high but the node was mature enough. I think the results that X Elite showed were insane if true (big if). I don't know how much Nuvia's next gen archs will evolve but i am not so optimistic for Intel if Lion Cove is something like 5-10% IPC over Raptor Cove. If you think about it ARL could be on Intel4 with a 5-10% IPC increase over Raptor Cove and some increases in clocks since the node seems fine. The CPU tile was really small, they could easily add stuff. Also if Lion Cove goal was some small IPC increase (5-10%) wait to see Intel having the smallest cores in the market.

4) AMD released their new APUs, they seem to be pretty good in terms of perf vs MTL. I hope Zen 5 end up being good like Zen 4 did.

 

[uzzi38]

LNC being barely faster that RPL were projections probably based on really old 20A targets. Obviously most stuff we are talking here are rumors and assumptions. Think about it.

It is true that those performance predictions are out of date, it's untrue that they're likely based on 20A silicon. Firstly, Intel barely expects any difference between 20A and Intel 3 results, secondly even back then the node choices would have been made.

Golden Cove (2021)
Raptor Cove = Golden Cove+
Redwood Cove = ~Raptor Cove
Lion Cove = Raptor Cove+ (2024-2025)

That's bullshit. 4 years the same arch for P cores?

Nobody's claiming or expecting that. I've made my own personal expectation (note: this is not a leak, just an expectation) is that LNC is targeting the same ~18% IPC uplift we've come to expect from a new core produced by Intel. But remember, those slides were indicating a ~10% ST performance uplift over RPL (5.8GHz). So with my expectation as a basis, it would imply Intel were expecting a clock regression at the time likely down to ~5.3 - 5.4GHz. I hope that doesn't sound like something totally absurd?

By the way, I fully expect Intel to actually beat that ~10% ST performance uplift, I wouldn't be surprised if it was actually conservative due to them not being totally confident on how high they could get LNC to clock. It's the first time they're trying to hit such high clocks on an external node after all.

Also if Lion Cove is so weak that LNL will end up bad, it wont be able to even beat X Elite in ST.

I mean, it is what it is. I'm just going to say it now though: I highly doubt X Elite will be the fastest performing mobile part for ST (lets take Geekbench as a basis for this one, as it's the best benchmark we can probably expect swift results from reviewers in), so even if LNL can't remain ahead of it, just the simple facts that: 1. it's x86, so app compatibility won't be a concern and 2. it's an Intel product, meaning volume wise it'll likely far outstrip all of it's competitors will mean LNL will have a very solid place in the market.

Then moving to desktop. 14th Gen is basically 13th Gen with DLVR and crazier clocks. X3D crashes them at gaming. Zen 5 will have V-cache. ARL will have clock regressions compared to 14th Gen which means if we are talking about a ~5% IPC over RPL, i dont see it beating even 14th Gen in gaming.

I wouldn't be concerned about IPC/Clock speed shenanigans if I were you, I'd be more concerned about IOSF and ring clocks. That's the real sore spot on MTL, hopefully it doesn't carry through to ARL (I actually don't have much hope).

 

[SiliconFly]

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[AMDK11]

1) Not a comp arch guy but small changes from Golden -> Redwood could be stuff associated with newer Ram or with the Layout. Alder L and Raptor L were monolithic designs and MTL is Tile based.

2) Depending your node's capabilities, your time and the capital that you allocate you can set different IPC targets. Raptor Lake was not an expensive arch to design. Meteor Lake was expensive in terms of designing and manufacturing because they moved from monolithic arch to tiles and packaging.

3) We don't know how far the clocks can be pushed for 3NB. Zen 4 pushed the clocks really high but the node was mature enough. I think the results that X Elite showed were insane if true (big if). I don't know how much Nuvia's next gen archs will evolve but i am not so optimistic for Intel if Lion Cove is something like 5-10% IPC over Raptor Cove. If you think about it ARL could be on Intel4 with a 5-10% IPC increase over Raptor Cove and some increases in clocks since the node seems fine. The CPU tile was really small, they could easily add stuff. Also if Lion Cove goal was some small IPC increase (5-10%) wait to see Intel having the smallest cores in the market.

4) AMD released their new APUs, they seem to be pretty good in terms of perf vs MTL. I hope Zen 5 end up being good like Zen 4 did.

Redwood Cove was supposed to be a refresh of GoldenCove with a 5-10% percent increase in IPC. IPC RedwoodCove was killed by the RAM controller in a separate tile.

Therefore, Intel reports that GraniteRapids increased the IPC for RedwoodCove, since Xeon has been tile-based since SapphireRapids.

MeteorLake in its current form loses compared to the monolithic RaptorLake by dividing the system into tiles.

 

[AMDK11]

I think LNC is the first iteration of the new core design that was developed under Jim Keller's supervision.


Personally, I think we're never gonna see SMT in client henceforth. Not worth the trouble. It's complexity leads to too many security headaches and it actually kicks in only when all the cores are already fully saturated. Better to have more physical cores instead (like 6+8 or 8+24).

I dare say that GoldenCove was created under the supervision of Jim Keller. Jim Keller was hired by Intel in 2018, and AlderLake launched in 2021. The only thing Keller had no say in was SunnyCove, whose project was completed.

In 2017, Intel was assembling a new team for a new processor project and most likely for the AlderLake (P Core + e Core) and GoldenCove + Gracemont projects.

As for SMT, it may be enabled in the ArrowLake refresh, but it may also happen that SMT remains only for Xeon. We don't know this for 100%. Intel hasn't officially confirmed anything yet.

I believe with 90% confidence that SMT physically exists in LionCove.

 

[dullard]

Assuming it reflects well in the real world, aren't we looking at LNL top part (with 8 Xe2 cores) doubling the performance of MTL top part (with 8 Xe1 cores) ???

I've seen rumors ranging from slightly lower iGPU performance to double performance. But, and this is key, these rumors are with significantly lower power ratings. The only Meteor Lake with 8 Xe1 cores are the top MTL-H chips (20 W to 65 W TDP). But Lunar Lake will do that with 8 W to 30 W TDP. Like others have said, it comes down to how much power you have and how much of that is pushed to the iGPU.

The memory being on-die and at a much higher speed (8533 for LNL vs 6400 for MTL) will help a lot if the iGPU is given enough power to use it.

 

[Ghostsonplanets]

I dare say that GoldenCove was created under the supervision of Jim Keller. Jim Keller was hired by Intel in 2018, and AlderLake launched in 2021. The only thing Keller had no say in was SunnyCove, whose project was completed.

I think it's very unlikely that GLC was created under Keller. He probably had some supervision in the later stages once he was at Intel, but very small stuff.

Need to remember that Intel was stuck for 5 years due to node issues. But IDC was already designing their uArchs well in advance because they needed to be ready for the 10nm transition, which never happened on the original timelines. (I'm not saying things haven't changed, but the ground layout was already set before the issues turned widespread)

I'd even argue that we're still seeing late 2010's designs from both Intel and AMD. Z5 was already being worked on by 2018 if we go by Clark interview. Lion Cove is probably on a similar timeline, if not even earlier.

If Keller had any significant contribution, it was probably on the fabled Royal Core. But, as Adroc, Exist and others have said, we might not even see Royal due to political issues at Intel.

So I guess we're stuck wrt "Next Big thing" until Glen Hilton reveals the "Exciting high performance project". Is it Panther Cove/Nova Lake? Something later?

 

[SpudLobby]

I would say the same for Crestmont. They better deliver 35+% IPC on Lion Cove compared to Raptor cove.

Lol

 

[SiliconFly]

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[SiliconFly]

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[Ghostsonplanets]

I think it starts with Panther Lake, then Diamond Rapids (and then Nova Lake)...

PTL = Cougar Cove/Lion Cove +. What is Diamond Rapids using? LNC or PTC?

Apparently, it was MTL he was working on.

Maybe MTL was supposed to use the cancelled Ocean Cove while Keller was there and when he left, they scrapped it altogether and changed it to GLC ++/Redwood Cove.

 

[SiliconFly]

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[SiliconFly]

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