Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[SiliconFly]

Don't you think it's highly worrying that LNC is supposed to be a ground up new design but supposedly already larger than RWC?

Similar to Apple Silicon. The P cores are way too larger than the corresponding E cores. Probably for higher ST performance.

 

[ondma]

If the initial leaks are accurate, it looks like LNC is a disaster for intel.

What an irony it would be if Intel was Keller's first botched architecture. Of course, it could be that there was simply too much corporate resistance/infighting to allow him to implement the design he really wanted.

 

[Saylick]

Isn't this what Intel wants though, large P cores with E cores around it

Even if Intel wants to keep that setup in the long run, they would want to make the P cores area competitive to all the competition out there.

Precisely. It's not about purely heterogeneous applications here. You can bet your top dollar that Intel wants to be competitive in the server space again, and a heterogeneous server SKU simply isn't something anyone wants. P cores have to offer good perf/area or else you get slaughtered in the high-end computing server space.

 

[H433x0n]

Don't you think it's highly worrying that LNC is supposed to be a ground up new design but supposedly already larger than RWC?

I think this is a really dumb metric - so what if it’s bigger? The size of the core doesn’t mean anything without any of the accompanying data. It’s entirely possible LNC is a larger core than RWC but also has a better PPA (Power, Performance, Area).

What if it’s 25% larger but has same clocks as RWC and has 19% better IPC? That’d be considered a win in PPA.

What if it’s 60% larger but only gets an 18% IPC bump? Then that’s a pretty big fail.

 

[moinmoin]

I think this is a really dumb metric - so what if it’s bigger? The size of the core doesn’t mean anything without any of the accompanying data. It’s entirely possible LNC is a larger core than RWC but also has a better PPA (Power, Performance, Area).

What if it’s 25% larger but has same clocks as RWC and has 19% better IPC? That’d be considered a win in PPA.

What if it’s 60% larger but only gets an 18% IPC bump? Then that’s a pretty big fail.

The point is that Intel's P cores are huge without the performance to show for it relative to their competition in the market. I'd consider area efficiency a low hanging fruit that can be picked once a true new fully ground up design is being done. Now LNC is called a new ground up design, and supposedly still bigger than RWC.

 

[Abwx]

What if it’s 60% larger but only gets an 18% IPC bump? Then that’s a pretty big fail.

That would still be a relative win since it s impossible to extract 18% better IPC with just 18% more transistors unless there were ground touching hanging fruits all around the tree.

Nowadays transistors counts are no more published but i would be curious for the numbers inflation since SKL/Zen1, i bet there s 2 x more transistors while we are far from 2 x the perfs.

 

[AMDK11]

I'm 99% sure LionCove will be larger than RedwoodCove in transistor count. I think it's about 35-50% larger at +20-25% IPC.

We look at AMD cores in terms of area, which is wrong because we don't know the transistor-per-core data, which makes comparisons difficult. AMD cores may simply be made up of more densely packed transistors, but that doesn't mean they contain significantly fewer transistors than Intel cores. Although I admit the possibility that Intel has more complex cores, without data on the number of transistors per core, comparison is not possible.

In the case of LionCove, Intel can make far-reaching and aggressive optimizations of a completely new project from scratch. AMD did something similar with Zen3. Unless there is a lot of logic in Intel's cores for the NSA, which is practically no longer present in Zen and can be gotten rid of in LionCove

Coming back to the ArrowLake-S tests, I am of the opinion that Intel's simulation tests say nothing about IPC. There is no data regarding clock speed, only the same number of Raptor and Arrow cores with similar power consumption.

There may well be a much larger IPC jump but it will be largely lost due to the much lower clock speed. Let's hypothetically assume that LionCove reaches a maximum of 3.5-4GHz and is 5-10% faster than RaptorCove. It would be nice because it would prove the great work and design skill of Intel teams, but the expectations would be too ambitious.More realistically, a slightly lower clock speed and ST 10-15% faster. We will soon find out whether LionCove is at least at the level of SunnyCove and GoldenCove in terms of expansion and IPC gains.

 

[Ajay]

If the initial leaks are accurate, it looks like LNC is a disaster for intel.

What an irony it would be if Intel was Keller's first botched architecture. Of course, it could be that there was simply too much corporate resistance/infighting to allow him to implement the design he really wanted.

He was trying to update the entire design and development process at Intel (like he did at AMD) before even getting to significant architectural changes. AMD was pretty lean and mean when he came in, so that process went along pretty fast. At Intel, it was dragging on because of institutional resistance. Getting interdependent groups to fully cooperate and get on the same page was, apparently, a ball buster.

 

[H433x0n]

I'm 99% sure LionCove will be larger than RedwoodCove in transistor count. I think it's about 35-50% larger at +20-25% IPC.

We look at AMD cores in terms of area, which is wrong because we don't know the transistor-per-core data, which makes comparisons difficult. AMD cores may simply be made up of more densely packed transistors, but that doesn't mean they contain significantly fewer transistors than Intel cores. Although I admit the possibility that Intel has more complex cores, without data on the number of transistors per core, comparison is not possible.

In the case of LionCove, Intel can make far-reaching and aggressive optimizations of a completely new project from scratch. AMD did something similar with Zen3. Unless there is a lot of logic in Intel's cores for the NSA, which is practically no longer present in Zen and can be gotten rid of in LionCove

Coming back to the ArrowLake-S tests, I am of the opinion that Intel's simulation tests say nothing about IPC. There is no data regarding clock speed, only the same number of Raptor and Arrow cores with similar power consumption.

There may well be a much larger IPC jump but it will be largely lost due to the much lower clock speed. Let's hypothetically assume that LionCove reaches a maximum of 3.5-4GHz and is 5-10% faster than RaptorCove. It would be nice because it would prove the great work and design skill of Intel teams, but the expectations would be too ambitious.More realistically, a slightly lower clock speed and ST 10-15% faster. We will soon find out whether LionCove is at least at the level of SunnyCove and GoldenCove in terms of expansion and IPC gains.

The traditional IPC increase from Intel has been 18-19%.

Sunny Cove was 18% over Skylake with 352 ROB.
Golden Cove was 19% over Sunny Cove with 512 ROB

I’d be willing to bet Lion Cove is 18-19% IPC over Golden Cove with 750+ ROB since this seems to be their target.

Looks like 1T boost clocks will hit 5.4ghz (with a small chance of a bit more). This should basically give you an idea of what to expect from ARL, figure ~10% ST uplift depending on workload.

 

[DavidC1]

The traditional IPC increase from Intel has been 18-19%.

Sunny Cove was 18% over Skylake with 352 ROB.
Golden Cove was 19% over Sunny Cove with 512 ROB

I’d be willing to bet Lion Cove is 18-19% IPC over Golden Cove with 750+ ROB since this seems to be their target.

AMD and ARM doesn't need that much of an ROB increase to improve performance.

Here's another thing about Lion Cove though: 8-wide front end.

That's a dramatic increase, especially since x86 decoders increase in transistor count quadratically with issue-width. Lion Cove doesn't seem anything more than any other Intel generations - a simple widening of resources.

The only time the main Core line didn't get dramatically larger was with Pentium M. Core, Nehalem, Sandy, Haswell, Skylake, all increased core sizes significantly. ~50% per generation.

That would still be a relative win since it s impossible to extract 18% better IPC with just 18% more transistors unless there were ground touching hanging fruits all around the tree.

Abwx speaks the truth in this case. Transistor count/die size and performance follows the inverse square law, if architects do not take care in implementing new features very carefully.

I'd be disappointed if Lion Cove stops at just 20%. If decrease in clocks are true, it better be 30%, since you should get something from seriously decreasing clocks.

 

[DavidC1]

Intel introduced new ideas in Pentium M, and then in Core 2. Then in Sandy Bridge. Since then? Nothing. Without it you are bound by the inverse square law. 20% improvement = 1.2x1.2x = 1.44x increase in core area + power. You must also think, is a feature worth putting over having more caches instead?
Caches are also power efficient.

The original Netburst Pentium 4 had 20 stage pipeline, with 27 stages or so on a trace cache miss. If you hit it it's probably 17-18. For Golden Cove it's 19 stages with 2-3+ on a miss, and -2-3 on a hit from the uop cache. With extra transistors on hand, we're basically at original P4 levels now. With uop caches having a 60-70% hit rate, it's not awesome.

Golden Cove adds a pipeline over predecessor. That's 2-3% perf/clk they could have gained. Apple chips are what, 10, 11 stages? You are talking 20-30%(or more) perf/clk difference just on pipeline stages alone!

Clock differences are bigger, sure. But how long can they sustain this? You need extra transistors just for the extra pipelines. Then you need larger transistors so you can drive them.

You know well enough that's not happening in highly political environments like Intel.

This is a wrong assumption. If there's enough pressure(usually due to struggling finances brought on by a mediocre product), and reason to do it, they will switch teams. This is a guarantee, if they want to live.

I don't see the need to switch to an entirely new team though. They can change the mindset on Core development.

 

[AMDK11]

My guess is somewhat based on the changes to Skylake-SunnyCove-GoldenCove:
LionCove x86 core:
L1-I 64KB 16-Way
PBU BTB
L0 256
L1 8-10K
L2 14-16K
Decode x86 8-Way
Micro-Op cache 6-7K
196-224 Decode Queue
ROB 750-800
Integer Register File ~350
Integer Scheduler 128-144
17x pipeline
7xALUs/3-4FPUs
7xAGUs(4+3)
3xStore Data
Load 280-320, Store 144-180
L1-D 48KB 12-Way
L2 512KB(low latency) + 2.5MB
L3 4MB

 

[tamz_msc]

Entrust a capable OEM like Dell or Lenovo to make a capable unit by not rushing to be the first - unlike Asus, and Acer - and MTL shines bright:

Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance

Meteor Lake shoots for the stars

www.tomshardware.com

 

[Hitman928]

Entrust a capable OEM like Dell or Lenovo to make a capable unit by not rushing to be the first - unlike Asus, and Acer - and MTL shines bright:

Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance

Meteor Lake shoots for the stars

www.tomshardware.com

Some power numbers and/or AC vs battery performance would have been nice. Actual noise measurements and display uniformity would also have been nice. Hopefully notebookcheck gets one for a more complete review.

As for the laptop, another one with a very large battery. Seems well built though. I would expect it to be a little cheaper given the 125h and no OLED screen in the configuration but the big battery and metal chasis probably pushes the price back up a bit. Would be interesting to see against other, similarly configured RPL and Zen4 laptops.

 

[Thunder 57]

Entrust a capable OEM like Dell or Lenovo to make a capable unit by not rushing to be the first - unlike Asus, and Acer - and MTL shines bright:

Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance

Meteor Lake shoots for the stars

www.tomshardware.com

Commentators disagree:

Review - Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance

Lenovo’s IdeaPad Pro 5i isn’t perfect, but it is a well-rounded entry in the ultraportable space. Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance : Read more

forums.tomshardware.com

But go on thinking that MTL "shines bright". Nevermind the price.

 

[DrMrLordX]

Entrust a capable OEM like Dell or Lenovo to make a capable unit by not rushing to be the first - unlike Asus, and Acer

Woulda been nice if the 7840u unit had also been a Dell or Lenovo. The one used in comparison is an Acer.

 

[tamz_msc]

Commentators disagree:

Review - Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance

Lenovo’s IdeaPad Pro 5i isn’t perfect, but it is a well-rounded entry in the ultraportable space. Lenovo IdeaPad Pro 5i review: Meteor Lake dazzles on performance and endurance : Read more

forums.tomshardware.com

But go on thinking that MTL "shines bright". Nevermind the price.

Price is absolutely within reason considering the performance and features.

Why would I care what other commentators think?

 

[Thunder 57]

Woulda been nice if the 7840u unit had also been a Dell or Lenovo. The one used in comparison is an Acer.

Doesn't fit the narrative.

 

[tamz_msc]

Doesn't fit the narrative.

As opposed to what, the counter-narrative?

 

[Thunder 57]

Price is absolutely within reason considering the performance and features.

Why would I care what other commentators think?

Because you are wrong, about everything? "MTL shines bright". Tell me you honestly have no bias?

 

[tamz_msc]

Woulda been nice if the 7840u unit had also been a Dell or Lenovo. The one used in comparison is an Acer.

Dell doesn't have Phoenix-U as AMD probably can't keep up with supply, considering the market position of Dell.

As for Lenovo, they have weird things going on with availability of specific models across the Atlantic.

 

[tamz_msc]

Because you are wrong, about everything? "MTL shines bright". Tell me you honestly have no bias?

LoL, and you are unbiased?

 

[Thunder 57]

LoL, and you are unbiased?

Of course not. I will at least admit it though. I try to be fair but Intel has been a turd sandwich lately.

 

[tamz_msc]

Of course not. I will at least admit it though. I try to be fair but Intel has been a turd sandwich lately.

So what if I'm biased too?

 

[Thunder 57]

So what if I'm biased too?

More power to you. I have no problem with that. But the fact that you bought a Rocket Lake CPU? Hell, even I didn't bother giving the time to Bulldozer and went Intel.