Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[RTX2080]

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core, but it cause some mobo function like M2 SSD misfunction the SMT was turned of on initial ES ARL SKUs.
Some terminology/key words are expunged(by yuuki_ans?) and leave blank, but it is easy to guess though.

 

[Dayman1225]

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core, but it cause some mobo function like M2 SSD misfunction the SMT was turned of on initial ES ARL SKUs.
Some terminology/key words are expunged(by yuuki_ans?) and leave blank, but it is easy to guess though.

View attachment 92133

I’m understanding it a bit differently, I’m reading it as the 8c 8t P Cores(“IA cores”) are disabled in bios due to instability bug with only e cores enabled

 

[SiliconFly]

That website is cancer. Remember when they said Zen would have 512MB of L3 cache? Years before 3D cache was a thing.

That website is trash. But the yuuki_ans leak looks legit.

These documents which are leaked by yuuki_ans seems imply the Hyperthreading(SMT) is still there in the ARL P core.

It clearly states 8 P cores / 8 Threads. So no HT. (IA -> P cores)

 

[Dayman1225]

I’d also like to point out this is “pre alpha” probably for power on and early validation. So it is not ES1 or ES2. Assuming it says 3.5Ghz, that is quite good for Skymont E cores on such an early chip

 

[DrMrLordX]

Source?
Cause someone just mentioned Intel has 288cores planned...

IIRC they showed a 2S system with 2 x 144C, but well, we should have some news sooner or later.

Last I saw, the 288c Sierra Forest system was 2P or like Cascade Lake-AP (2P in one socket).

In other words, the high core-count dice had been cancelled.

edit @QuickyDuck beat me to it

 

[Abwx]

Last I saw, the 288c Sierra Forest system was 2P or like Cascade Lake-AP (2P in one socket).

In other words, the high core-count dice had been cancelled.

edit @QuickyDuck beat me to it

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

 

[DrMrLordX]

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

Tell that to Intel. It wasn't my idea.

 

[SiliconFly]

If 144C require 360W it doesnt make sense to cram 288C for this TDP, that s silicon waste as long as it s with the same process.

Bergamo is around 400W. So, SF 288C can comfortably go up to 450W which should be quite sufficient.

 

[eek2121]

That website is cancer. Remember when they said Zen would have 512MB of L3 cache? Years before 3D cache was a thing.

The site IS garbage, but all future Intel chips will have higher base clocks thanks to process improvements. Even Meteor Lake has higher base clocks.

 

[Anhiel]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

 

[S'renne]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

That's what the E cores are for, and ARM CPUs doesn't use SMT but is still competitive in MT

 

[SiliconFly]

It does look like only HT has been turned off rather than a specific ST only design. Welp, I guessed as much last year.
It's been shown before Skylake/ADL without HT gains ~24% (outliers 31%) for ST. Since the MT gains aren't as large as Zen's ofc it means Intel's has a bigger loss in MT mode for the 1st thread and 2nd thread. Since Zen is able to keep higher rates for the 1st and 2nd threads and only gets ~12% w/o SMT. Zen would have more too lose so this cheap trick won't work for Zen. Sooner or later HT will have to return imho.

LNC is a grounds up new design. So, HT hasn't been turned off. It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT. So, HT isn't coming back.

And considering the numerous cores CPUs have these days, HT doesn't make sense anymore. HT is purely for MT gains, and it offers performance benefit only when all the existing cores are already maxed out. HT based thread context switching is significantly faster when compared to a OS based context switch. That is it's sole purpose. Throwing more E cores into the mix and improving the performance of E cores should take care of MT perf without HT. Keeps P core design neat & clean.

Also, I remember reading that the new LNC P cores are going to be larger than RWC P cores! Don't know how far it's true, but looks like that might be the case. LNC's primary focus seems to be ST performance more than MT performance.

 

[trivik12]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

https://twitter.com/x/status/1747981927020449985

 

[SiliconFly]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

If it's MTL-U refresh on intel 3, then it's not worth anybody's time.

 

[SpudLobby]

If it's MTL-U refresh on intel 3, then it's not worth anybody's time.

Eh.
What actually sucks is that it’s MTL, not Intel 3. That part is interesting. Should see see real performance/watt and density gains. Not enough to take away from the primary issue with MTL — or ARL’s crap — but still. Academically interesting.

 

[trivik12]

Since Intel 3 is refined Intel 4, clock speeds should be higher. That said I am not sure about Intel's strategy here. Anyway we will know details probably around September when Intel On event is hosted.

 

[moinmoin]

Keeps P core design neat & clean.

Also, I remember reading that the new LNC P cores are going to be larger than RWC P cores!

I personally wouldn't think of calling those monster P cores whose size was the reason to introduce E cores to begin with "neat & clean". Also I find it really odd that HT gets removed but the design apparently is not redone enough to make the area usage any more efficient.

 

[gdansk]

Arrow Lake is meh

How do you know this?

 

[coercitiv]

Also I find it really odd that HT gets removed but the design apparently is not redone enough to make the area usage any more efficient.

I would not be surprised if SMT circuitry is still there. Remember when they told us they had removed AVX512 transistors from Lakefield?

Knowing that Lakefield was going to have to take the lowest common denominator from the two core designs, Intel probably should physically removed the very bulky AVX-512 unit from the Sunny Cove core. Looking at the die shot, it's still there - there was some question going into the recent disclosures as to whether it would still be there, but Intel has stated on the record repeatedly that they removed it. The die shot of the compute silicon shows that not to be the case.

 

[poke01]

How do you know this?

I am guessing from the way Intel is projecting it.

 

[uzzi38]

SquashBionic is saying ARL-U is Intel 3. Not sure if he is reliable. But I see multiple articles quote him as source.

https://twitter.com/x/status/1747981927020449985

Bionic literally has slides on hand (that I've seen, so I know they exist). He's as reliable as you can ask for.

 

[SiliconFly]

...I find it really odd that HT gets removed but the design apparently is not redone enough...

Wrong. LNC is a grounds up new design started under Keller's supervision. So, HT hasn't been "removed". It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT.

 

[moinmoin]

Wrong. LNC is a grounds up new design started under Keller's supervision. So, HT hasn't been "removed". It was never implemented. Starting with LNC, they're trying to follow the likes of Apple Silicon which offers higher performance without HT or SMT.

Don't you think it's highly worrying that LNC is supposed to be a ground up new design but supposedly already larger than RWC?

 

[S'renne]

Don't you think it's highly worrying that LNC is supposted to be a ground up new design but supposedly already larger than RWC?

Isn't this what Intel wants though, large P cores with E cores around it

 

[moinmoin]

Isn't this what Intel wants though, large P cores with E cores around it

Even if Intel wants to keep that setup in the long run, they would want to make the P cores area competitive to all the competition out there.