Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[uzzi38]

Could you please show us the other slides you mention?

Oh, I totally forgot to come back to this.

Here. I'm not leaking anything that's new, so I've censored out anything that has even the slightest bit of being actually new information. Deal with it.

 

[inf64]

That is pretty abysmal ST gain for Arrow lake, I find it very hard to believe it. The only way this could be true is that Arrow Lake clocks waaay lower than Raptor Lake and this nullifies the IPC gains.

 

[S'renne]

That is pretty abysmal ST gain for Arrow lake, I find it very hard to believe it. The only way this could be true is that Arrow Lake clocks waaay lower than Raptor Lake and this nullifies the IPC gains.

Probably if Intel decides to focus on mainly efficiency over absolute performance due to inherent design flaws I think

 

[SiliconFly]

Oh, I totally forgot to come back to this.

Here. I'm not leaking anything that's new, so I've censored out anything that has even the slightest bit of being actually new information. Deal with it.

View attachment 85836

When I last mentioned that ARL may get Battlemage as it's already up & running, people said no. Many believe ARL is actually getting Alchemist+. But this slide says otherwise.

So, is this slide legit? Is ARL getting Battlemage?

 

[uzzi38]

When I last mentioned that ARL may get Battlemage as it's already up & running, people said no. Many believe ARL is actually getting Alchemist+. But this slide says otherwise.

So, is this slide legit? Is ARL getting Battlemage?

It very clearly says discrete GPU, not integrated.

 

[dullard]

Oh, I totally forgot to come back to this.

Here. I'm not leaking anything that's new, so I've censored out anything that has even the slightest bit of being actually new information. Deal with it.

Thanks for sharing. I have not seen that before. So you were talking about gaming performance. That helps clarify. Although it doesn't specify if that "perf gain" refers to IPC, clocks, or the combination of both.

 

[inf64]

Thanks for sharing. I have not seen that before. So you were talking about gaming performance. That helps clarify. Although it doesn't specify if that "perf gain" refers to IPC, clocks, or the combination of both.

Well ST gains must be a cumulative effect of clocks and IPC, or else they would specify IPC (or clock). Historically, intel used ST uplift this way, correct me if I'm wrong.

 

[JoeRambo]

Arrow-Lake-S perf seems to be spot on where earlier leaks ( internal perf estimate? ) predicted.

I am not sure what people expect from more iCache, 3MB of L3 and similar L3 cache setup? It's same core, but enabled to get better MT performance.
Absolutely nothing radical that would increase perf in unexpected way like 100MB of L3 or completely new design of P core -> that will have to wait for redesign.

I think the people who expect wonders from Zen5 might be also surprised in performance increase that is smaller than expectation in first generation of new core.

 

[inf64]

Arrow-Lake-S perf seems to be spot on where earlier leaks ( internal perf estimate? ) predicted.

I am not sure what people expect from more iCache, 3MB of L3 and similar L3 cache setup? It's same core, but enabled to get better MT performance.
Absolutely nothing radical that would increase perf in unexpected way like 100MB of L3 or completely new design of P core -> that will have to wait for redesign.

I think the people who expect wonders from Zen5 might be also surprised in performance increase that is smaller than expectation in first generation of new core.

Although I agree with almost everything you said, I think you are wrong regarding Zen 5. Zen 5 might disappoint when it comes to peak GHz target, but IPC jump should be higher than what Zen 3 brought - and this would put it in the Bulldozer -> Zen 1 category of more than 20% IPC jump between two gens.

 

[ondma]

Arrow-Lake-S perf seems to be spot on where earlier leaks ( internal perf estimate? ) predicted.

I am not sure what people expect from more iCache, 3MB of L3 and similar L3 cache setup? It's same core, but enabled to get better MT performance.
Absolutely nothing radical that would increase perf in unexpected way like 100MB of L3 or completely new design of P core -> that will have to wait for redesign.

I think the people who expect wonders from Zen5 might be also surprised in performance increase that is smaller than expectation in first generation of new core.

Why do you say that? Do you have any recent leaks?
I thought ARL was supposed to be the first itineration of the new core design? It doesn't make sense that they could not get hyperthreading working (if rumor is correct) if it was the same basic core as ALD/RL.

 

[Kepler_L2]

Arrow-Lake-S perf seems to be spot on where earlier leaks ( internal perf estimate? ) predicted.

I am not sure what people expect from more iCache, 3MB of L3 and similar L3 cache setup? It's same core, but enabled to get better MT performance.
Absolutely nothing radical that would increase perf in unexpected way like 100MB of L3 or completely new design of P core -> that will have to wait for redesign.

I think the people who expect wonders from Zen5 might be also surprised in performance increase that is smaller than expectation in first generation of new core.

It's a 30-50% wider core than GLC. A 5% improvement is extremely disappointing.

 

[inf64]

It's a 30-50% wider core than GLC. A 5% improvement is extremely disappointing.

The only way 5% figure could be true is if the new core clocks topped at roughly 4.8-5Ghz for ST.

 

[SiliconFly]

Why do you say that? Do you have any recent leaks?
I thought ARL was supposed to be the first itineration of the new core design? It doesn't make sense that they could not get hyperthreading working (if rumor is correct) if it was the same basic core as ALD/RL.

Yep. No hyper-threading means only one thing. It's LNC.

But the "no hyper-threading" thing is still a rumor.

 

[SiliconFly]

It's a 30-50% wider core than GLC. A 5% improvement is extremely disappointing.

If ARL-S isn't getting any noticeable performance improvement, then it's going to get a lot of improvement in power-efficiency. A lot!

Remember, ARL is in Intel 20A which has a massive PPW gain of 36% over Intel 4.

 

[A///]

Probably if Intel decides to focus on mainly efficiency over absolute performance due to inherent design flaws I think

And let AMD eat more of their lunch? That's a laughable thought.

 

[A///]

Do you have any recent leaks?

I imagine from his hind quarters. It's not the first time he's downplayed the reality that's coming in a few months.

 

[Geddagod]

I am not sure what people expect from more iCache, 3MB of L3 and similar L3 cache setup? It's same core, but enabled to get better MT performance

No.

or completely new design of P core

That's LNC. Though maybe not "completely" new design, it's just more the same of "wider, deeper, smarter"

thought ARL was supposed to be the first itineration of the new core design?

It's not Royal Core.

If ARL-S isn't getting any noticeable performance improvement, then it's going to get a lot of improvement in power-efficiency. A lot!

That's not necessarily true.

Remember, ARL is in Intel 20A which has a massive PPW gain of 36% over Intel 4.

That's not how it works.

 

[A///]

Royal Core.

Much like who ate the last piece of pie, what's going on with this?

 

[SiliconFly]

That's not how it works.

For the same architecture, it does. For a better architecture, even more.

 

[H433x0n]

Oh, I totally forgot to come back to this.

Here. I'm not leaking anything that's new, so I've censored out anything that has even the slightest bit of being actually new information. Deal with it.

View attachment 85836

is that 1.05 over RPL-R? That puts it at +10% over RPL which still isn’t great but it’s better than nothing.

 

[SiliconFly]

is that 1.05 over RPL-R? That puts it at +10% over RPL which still isn’t great but it’s better than nothing.

Hard to say whether it's RPL or RPL-R. Absolutely no context. We shouldn't be using this info until we have better clarity.

 

[Glo.]

And let AMD eat more of their lunch? That's a laughable thought.

Mobile is where the battle will be the biggest and toughest between AMD and Intel in upcoming years.

 

[dullard]

Remember, ARL is in Intel 20A which has a massive PPW gain of 36% over Intel 4.

Do note: that your math is on the high end of what to expect.

Intel 3 is supposedly ~18% more performance per watt compared to Intel 4 (everything else being equal)
Intel 20A is UP TO 15% more performance per watt compared to Intel 3 (everything else being equal)

So crude math would be 1.18 * 1.15 = 1.357 or 35.7% more performance per watt (everything else being equal). So right off the bat you rounded up. But also you ignored the UP TO part. So, think of 35.7% as one of the better case scenarios (everything else being equal).

But of course, not everything is equal, so Intel could ramp up the frequency. Or Intel could add other features that use energy. Etc. All of those would toss performance per watt out the window. That and we still have the rumor that not all Arrow Lake is on 20A.

 

[SiliconFly]

Mobile is where the battle will be the biggest and toughest between AMD and Intel in upcoming years.

If Intel's hyper-focused on efficiency, then ARL mobile's power-efficiency will be off the charts due to 20A. Will definitely have a huge impact in mobile.

ARL-S (desktop) can also have a huge PPW improvement. But without much performance improvement how that translates into sales is a big if.

 

[adroc_thurston]

will also have a huge PPW improvement

15% nT perf ISO core count is bad and you know it.