Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[A///]

summary?

 

[H433x0n]

at least double digits is a bit far from ~20%.
Isn't ~20% from MLID?
Wonder if EMR fixes L3 bandwidth problems SPR faces

I’ve got no idea what MLID claims about EMR.

It’s a notable bump in performance from being able to squeeze more performance from the same power budget. There were multiple changes to it that contribute to better PPA, it’s using a better version of the Intel 7 node, there is less overhead in the layout of the XCC configurations and lastly there’s a very small IPC uplift from the increased L3$.

 

[H433x0n]

Mesh clock is literally going down so lol. lmao.

The good news is that we'll have a definitive answer in less than 6 months.

 

[adroc_thurston]

The good news is that we'll have a definitive answer in less than 6 months.

Yea and EMR is whatever.
Has less catastrophic edge cases than SPR but once again, whatever-tier product.

 

[H433x0n]

Yea and EMR is whatever.
Has less catastrophic edge cases than SPR but once again, whatever-tier product.

I’m not making extraordinary claims. I’m being relatively sober / grounded with Intel’s DC lineup. I have to take exception with 2 things you claimed though:

I’m certain that EMR performance over SPR is better than margin of error and GNR-AP will outperform Genoa.

I don’t claim to know anything about Zen 5 so I’m not going to make predictions on how GNR stacks up against it. Those 2 points I outlined I am certain about though.

 

[adroc_thurston]

I’m certain that EMR performance over SPR is better than margin of error

In cases where SPR is a catastrophe yea, in SPECint rate no.

GNR-AP will outperform Genoa.

Yea it better do given it's 150W more.

 

[A///]

I’ve got no idea what MLID claims about EMR.

doesn't matter, they're from his derriere.

 

[H433x0n]

In cases where SPR is a catastrophe yea, in SPECint rate no.

I'm not talking about SPECint. A higher SPECint & SPECfp score is not the primary goal. I'm talking about the cumulative result of all tests performed by Phoronix for example.

Yea it better do given it's 150W more.

This is what you said a few pages back:

HAHAHAHHAHAHAHA ohohohohohoohhohoho jesus.
GNR is approximately competitive with maybe Genoa if it's lucky.

I'll even be bold and say that it will outperform Genoa when comparing like for like (core counts & power consumed).

Which to be honest still isn't even that bold, I'm fairly confident these words won't come back to bite me.

 

[adroc_thurston]

I'm not talking about SPECint.

That's how both vendors guide their socket perf deltas, lol.
It's a simple and easily understandable metric.

A higher SPECint & SPECfp score is not the primary goal. I'm talking about the cumulative result of all tests performed by Phoronix for example.

Yea it's a less catastrophic design than SPR but that's all there is to it.

This is what you said a few pages back:

Yea, it's gonna be lucky to be competitive with Genoa, given how much faster Genoa is in SPECint rate over Milan/SPR.

that it will outperform Genoa when comparing like for like (core counts & power consumed).

lol no chance.

 

[mikk]

Intel Meteor Lake Xe-LPG iGPU reportedly boosts up to 2.2 GHz, slightly more compute power than Radeon 780M - VideoCardz.com

Intel Meteor Lake Xe-LPG graphics currently boost up to 2.2 GHz The competition in integrated graphics is heating up. Intel is in the final stages of preparing its Meteor Lake chips for launch later this year. The upcoming mobile Core Ultra series will introduce an entirely new architecture...

videocardz.com

Don't know if this has been posted yet, but iGPU clocks are nice. A little disappointed in the ST max frequency clock based on previous rumors that indicate it would reach >5GHz, but who knows maybe the QS isn't the -H series or something (though that might just be copium on my part lmao).
I think a ST regression is becoming more and more likely looking at clocks, but for the overall laptop, if they manage to reduce CPU power consumption during gaming, overall game fps might increase if they funnel some extra power over to the dGPU.

This is from an engineering sample, I think it's obvious they will target 5 Ghz. ST probably within +-5% to Raptor Lake. It's not a big deal, the bigger deal would be the efficiency improvements under load which we don't know yet.

 

[Abwx]

I'll even be bold and say that it will outperform Genoa when comparing like for like (core counts & power consumed).

If they could only double the core count from Intel 7 to the claimed Intel 3 it means that the latter should be more reasonably called Intel 5 and have comparable density to TSMC s N5, from 7 to 3 there s theoricaly 5x density improvement, wich is obviously not the case, that s just a marketing gimmick to make people think that they have closed the gap with TSMC s most advanced process wich is N3.

Beside the fact that they need a 500W TDP is indicative that the perf/watt is not better than said TSMC s process, so that s bold claim that it should outperform AMD s Genoa, we wont even talk of Bergamo wich is 360W for 128C, the same core count as a 500W GNR.

 

[adroc_thurston]

If they could only double the core count from Intel 7 to the claimed Intel 3 it means that the latter should be more reasonably called Intel 5 and have comparable density to TSMC s 5N, from 7 to 3 there s theoricaly 5x density improvement, wich is obviously not the case, that s just a marketing gimmick to make people think that they have closed the gap with TSMC.

Beside the fact that they need a 500W TDP is indicative that the perf/watt is not better than said TSMC s process, so that s bold claim that it should outperform AMD s Genoa, we wont even talk of Bergamo wich is 360W for 128C, the same core count as a 500W GNR.

The issue is less node and more cores themselves.

 

[H433x0n]

If they could only double the core count from Intel 7 to the claimed Intel 3 it means that the latter should be more reasonably called Intel 5 and have comparable density to TSMC s N5, from 7 to 3 there s theoricaly 5x density improvement, wich is obviously not the case, that s just a marketing gimmick to make people think that they have closed the gap with TSMC s most advanced process wich is N3.

Beside the fact that they need a 500W TDP is indicative that the perf/watt is not better than said TSMC s process, so that s bold claim that it should outperform AMD s Genoa, we wont even talk of Bergamo wich is 360W for 128C, the same core count as a 500W GNR.

I’ve gotten into enough disagreements over Intel process nodes and how they will compete against TSMC.

Here’s all I can say: Intel 3 will be a significant improvement over the latest Intel 7 node. It’s not theoretically 5x more dense, it’s not even close to that figure. For that matter N7 to N3 is not 5x more dense either.

You’re not factoring in clocks to the equation nor the core characteristics of RWC+. To get >=120 RWC+ cores within a 500W power envelope is not at all comparable to Bergamo.

 

[moinmoin]

But if it's canceled, we would hopefully hear something during their earnings report.

Do we actually get public confirmations of cancellations? To me it seems most of the time either people just stop caring to ask and it fades into obscurity, or the name gets reused for something different.

AMD makes better cores than anyone else in the industry and you will learn it the hard way!

That's a bullish statement if there ever was one! Wrong thread though. Would you be willing to get into more details (whatever isn't risky but not widely known yet) in the dedicated Zen 5 thread? Considering Zen 5 is the first ground up Zen design by a newly financially potent AMD the possibilities are all there.

 

[adroc_thurston]

To get >=120 RWC+ cores within a 500W power envelope is not at all comparable to Bergamo.

It is, RWC's aren't that much faster per thread and power there is no good at all.
LNC is the interesting one and genuinely is a rather capable core but that's not what GNR has so...
Again, focus on client parts.
DCAI is totaled in both DC and, well, AI.

That's a bullish statement if there ever was one!

Yea I was kinda amazed when I saw Eldora A0 results.

Considering Zen 5 is the first ground up Zen design by a newly financially potent AMD the possibilities are all there

Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
Mikey C. wasn't joking about daydreaming the thing.

 

[H433x0n]

It is, RWC's aren't that much faster per thread and power there is no good at all.

You misunderstand what I'm trying to say. RWC & Zen 4C are not comparable cores, they weren't developed with the same design goals. This makes Bergamo a bad yardstick for comparing the Intel's nodes to TSMC.

Honestly, there is no way to make an accurate comparison at all considering how different Intel / TSMC processes are. Their means and methods are not directly comparable, both in the chemistry and also how they achieve scaling through DTCO. This is also true when comparing Intel and AMD architectures, they're so different that using it for any type of node comparison is meaningless. The closest we'll ever get will be ARL since Intel will have similar products on both internal and external nodes.

 

[adroc_thurston]

RWC & Zen 4C are not comparable cores, they weren't developed with the same design goals.

Well Zen4c is literally just Zen4, but clocks less.
Not really that different at all.

Honestly, there is no way to make an accurate comparison at all considering how different Intel / TSMC processes are. Their means and methods are not directly comparable, both in the chemistry and also how they achieve scaling through DTCO

Ehhh i3 will be offered as an IFS node so should be similar enough given any kind of IFS offering requires the node to support very much industry standard design flows.

The closest we'll ever get will be ARL since Intel will have similar products on both internal and external nodes.

Oh lol I have quite some news for you.

 

[Exist50]

It is, RWC's aren't that much faster per thread and power there is no good at all.
LNC is the interesting one and genuinely is a rather capable core but that's not what GNR has so...
Again, focus on client parts.
DCAI is totaled in both DC and, well, AI.

Yea I was kinda amazed when I saw Eldora A0 results.

Second, Zen3 was the first one.
Zen5 is by far a more ambitious one.
Mikey C. wasn't joking about daydreaming the thing.

Dude, I think you're working with incomplete information. That, or you're just feeding into the hype. Might want to tone it down a bit...

 

[adroc_thurston]

Dude, I think you're working with incomplete information

I know what I know, that's all there is to it.

That, or you're just feeding into the hype

There is no hype, Zen5 really is the best thing since sliced bread and Intel very much knows it now.
Even if it took two hyperscalers worth of reality checks.

 

[Exist50]

I know what I know, that's all there is to it.

Well it's not like we have any way to verify that claim. MLID says the same.

There is no hype, Zen5 really is the best thing since sliced bread and Intel very much knows it now.

That's exactly what I'm referring to...

 

[adroc_thurston]

Well it's not like we have any way to verify that claim

All you gotta do is talking to Intel ppl.

That's exactly what I'm referring to...

Yes, it was a rather rude awakening.

 

[Exist50]

All you gotta do is talking to Intel ppl.

I have (and AMD), and what I hear doesn't match the claims you're making.

 

[adroc_thurston]

I have (and AMD), and what I hear doesn't match the claims you're making.

No you haven't, then.
Turin socket perf targets are known for both 96c and 128c configs.

 

[Exist50]

No you haven't, then.
Turin socket perf targets are known for both 96c and 128c configs.

Then stick around this forum long enough for us to see. Because right now, all I'm seeing is unsupported hype.

 

[adroc_thurston]

Then stock around this forum long enough for us to see

It's not that much wait anymore, someone in China will inevitably leak their Turin testbench into the world.

Because right now, all I'm seeing is unsupported hype.

Yes obviously unsupported hype despite Si being sampled and perf targets being, well, final.