Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Saylick]

As Saylick explains it is just halving the reticle size. Instead of 26x33 it is 13x33 IIRC which while still 400+ mm^2 is pretty rectangular so the effective max for some designs is probably closer to 300 mm^2.

Everyone has known this is coming for years, and is one of the several reasons driving everyone to chiplet based designs.

26mm x 16.5mm, but yeah. Quite rectangular but not limiting for midsized dies. If your name is Nvidia, however, you're going to need to pivot within 3 years.

 

[A///]

26mm x 16.5mm, but yeah. Quite rectangular but not limiting for midsized dies. If your name is Nvidia, however, you're going to need to pivot within 3 years.

That falls in line with blackwell still being a monolothic die. Do you think nvidia would sooner move to chiplets on consumer or their pro hardware?

 

[mikk]

In this Anandtech article it claims they are

And after some digging....
you don't even have to believe Ian, here's a quote from the head of Intel's node development, Ann Kelleher herself

Essentially high NA EUV is going to intercept what ever node they can use it in. I'm assuming they have preparations for Intel 18A with and without High-NA, and probably the same for 16A. Intel 18A got pushed up to 2H 2024 for HVM ready, but we won't really be seeing products on Intel 18A until 2025.

This is outdated from 2021, better check out here: https://www.anandtech.com/show/17415/asmls-highna-update-coming-to-fabs-in-2024-2025

Anandtech is not so sure anymore:

But recently Intel pulled-in the start of18A production to the second half of 2024 and indicated that it could use ASML's Twinscan NXE:3600D or NXE:3800E for its 18A manufacturing, presumably via multi-patterning.

And actually they don't believe in it anymore which you can see in their selfmade roadmap: https://images.anandtech.com/doci/17344/IntelRoadmap_H1_2022b.png

In the latest big roadmap update from Intel there is nothing about 18A+High-NA, it's the opposite. They pretty much confirmed nodes up to 18A are using regular 0.33 NA EUV, you can find the original source here: https://www.intel.com/content/dam/w.../2022-intel-investor-meeting-process-tech.pdf

Your quote from 2021 is old and there was no confirmation for 18A either. She didn't say it will be introduced in a shipping mass volume node or 18A, it could mean anything. Anandtech and others back in 2021 simply assumed 18A will be using High-NA because of the timeline.

 

[A///]

Thanks mikk. I had looked at Gedda's post and knew I'd seen something newer than that because it didn't align with what I remember which isn' saying much with my memory. What would be the first product to use intel's new ribbon based gaafet and power delivery system? DrMrLord mentioned it a few weeks back but good luck trying to find a post. Would be it be Arrowlake assuming a 1h release or 2h if lunar mobile lake is 1h?

 

[Geddagod]

This is outdated from 2021, better check out here: https://www.anandtech.com/show/17415/asmls-highna-update-coming-to-fabs-in-2024-2025

Anandtech is not so sure anymore:


And actually they don't believe in it anymore which you can see in their selfmade roadmap: https://images.anandtech.com/doci/17344/IntelRoadmap_H1_2022b.png

In the latest big roadmap update from Intel there is nothing about 18A+High-NA, it's the opposite. They pretty much confirmed nodes up to 18A are using regular 0.33 NA EUV, you can find the original source here: https://www.intel.com/content/dam/w.../2022-intel-investor-meeting-process-tech.pdf

Your quote from 2021 is old and there was no confirmation for 18A either. She didn't say it will be introduced in a shipping mass volume node or 18A, it could mean anything. Anandtech and others back in 2021 simply assumed 18A will be using High-NA because of the timeline.

The article you are quoting from agrees that Intel 18A would use High NA if it comes out in time.
The quote you chose from the article doesn't show the full picture- here's some more context

So far, the only process technology confirmed to use ASML's High-NA tools is Intel's 18A node and that one was once scheduled to enter high-volume production in 2025, around the time when ASML starts to deliver its production High-NA EUV systems. But recently Intel pulled-in the start of18A production to the second half of 2024 and indicated that it could use ASML's Twinscan NXE:3600D or NXE:3800E for its 18A manufacturing, presumably via multi-patterning.
While Intel's 18A technology would greatly benefit from High-NA EUV tools, it looks like Intel does not necessarily need Twinscan EXE:5200 machines for this node. Usage of multi-patterning for commercial chips means a longer product cycle, lower productivity, higher risks, and potentially lower yields (though the latter is not cast in stone). Yet, it looks like Intel wants its 18A node to arrive as soon as possible, perhaps because it considers it a major tool that will allow it to recapture process technology leadership from TSMC. Consequently, Intel's updated plans are now to phase in High-NA tooling during 18A's lifecycle if the tools are completed on time.

So ye, Intel 18A has high NA and non-high NA versions, and would prob phase in Intel 18A high NA later in the development cycle.
What Ann's quote repeats this sentiment- high NA is not set in stone and could be used with Intel 18A, Intel 16A, etc etc. It all depends on when they get their tools, and they would want to phase it in as soon as possible for at the very least economic reasons, if not for the technical reasons of using the machine to learn about the process and use it in future nodes.
Intel 18A might not use high NA initially, but I would not be surprised if they phase it in eventually. Remember Intel claims, using the same slide, high NA is going to be HVM in 2025. So unless you think Intel 16 or Intel 17 is going to be HVM in 2025 (when clearwater forest is on Intel 18A most likely late 2025 and on client side Intel 18A ARL should just be released early 2025) I don't see any conflicts between what is being said officially by Intel and what is being speculated here.

 

[A///]

From anton to ann in one fell swoop.

 

[Geddagod]

Thanks mikk. I had looked at Gedda's post and knew I'd seen something newer than that because it didn't align with what I remember which isn' saying much with my memory. What would be the first product to use intel's new ribbon based gaafet and power delivery system? DrMrLord mentioned it a few weeks back but good luck trying to find a post. Would be it be Arrowlake assuming a 1h release or 2h if lunar mobile lake is 1h?

Internal Intel 3 node for backside power delivery, officially Intel 20A for both, prob going to in ARL. It seems to be pretty much impossible for Intel 20A to be out 2024, unless its at the very end of 2024 as a paper launch. Offc Intel could decide not to implement it in ARL too I assume, to derisk the development

 

[A///]

Internal Intel 3 node for backside power delivery, officially Intel 20A for both, prob going to in ARL. It seems to be pretty much impossible for Intel 20A to be out 2024, unless its at the very end of 2024 as a paper launch. Offc Intel could decide not to implement it in ARL too I assume, to derisk the development

Let's see Raptor refresh is coming by end of September whatever the final specs are on it. MTL mobile comes out sometime this year or next. I want to say there has been a year or two where Intel didn't release a major platform and it was pushed way to the end and launching early next year. A health intel firing on all pots would have released 2 major milestones in a year like they have a few times in the past. Arrowlake based on rumors I've read and been posted here uses a new approach to the design based on the Intel engineering day of 2020 or 2021... anyway it's a lot for a first generation product. the backside power delivery is a new feature but as is their new transistor tech. It's a lot on their plate. My only other guess is they do what you said but they're producing right now and testing long term to address issues. mtl es are in the wild as of 2 days ago. still no clue when they'd launch but if arrowlake is to follow those es and es leaks will be gold for anyone who can get their hands on them with the dev board or the prelim data. getting all this right is essential for Intel to catch up or lose more if they fail.

 

[Saylick]

That falls in line with blackwell still being a monolothic die. Do you think nvidia would sooner move to chiplets on consumer or their pro hardware?

I don't mean to derail the thread but to answer your question, I think Nvidia will delay moving to MCM, chiplets, or some form of advanced packaging for as long as possible. They'll start with their server hardware in the form of COPA, then if there's even a desire for it, they'll transition the top SKU (i.e. xx100 or xx102 class dies) as the flagship xx90 and xx90 Ti to the consumer side. Anything less than that can remain monolithic. MLID speculated that Nvidia might not even care in the near future that their top consumer SKU isn't some >500mm2 honking GPU because their game plan is to just win via software features, not raw horsepower outright. That, along the fact that they much prefer the margins in the enterprise space, means consumers are valued less and less to them moving forward.

 

[Geddagod]

Let's see Raptor refresh is coming by end of September whatever the final specs are on it. MTL mobile comes out sometime this year or next. I want to say there has been a year or two where Intel didn't release a major platform and it was pushed way to the end and launching early next year. A health intel firing on all pots would have released 2 major milestones in a year like they have a few times in the past. Arrowlake based on rumors I've read and been posted here uses a new approach to the design based on the Intel engineering day of 2020 or 2021... anyway it's a lot for a first generation product. the backside power delivery is a new feature but as is their new transistor tech. It's a lot on their plate. My only other guess is they do what you said but they're producing right now and testing long term to address issues. mtl es are in the wild as of 2 days ago. still no clue when they'd launch but if arrowlake is to follow those es and es leaks will be gold for anyone who can get their hands on them with the dev board or the prelim data. getting all this right is essential for Intel to catch up or lose more if they fail.

Backside power delivery is being tested on Intel 3 before Intel 20A. Idk what they mean by "internal node". Maybe they just have it in labs with no products using it?
I don't think ARL's structure is going to differ from MTL's, nothing like multiple compute tiles or anything imo. Jim thinks there's going to be 3D stacked cache somewhere on it though, but honestly I think if it is there, it's going to be cache on the interposer, which I believe? Intel tried with Ponte Vechio.

 

[Saylick]

Internal Intel 3 node for backside power delivery, officially Intel 20A for both, prob going to in ARL. It seems to be pretty much impossible for Intel 20A to be out 2024, unless its at the very end of 2024 as a paper launch. Offc Intel could decide not to implement it in ARL too I assume, to derisk the development

If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.

 

[Geddagod]

I don't mean to derail the thread but to answer your question, I think Nvidia will delay moving to MCM, chiplets, or some form of advanced packaging for as long as possible. They'll start with their server hardware in the form of COPA, then if there's even a desire for it, they'll transition the top SKU (i.e. xx100 or xx102 class dies) as the flagship xx90 and xx90 Ti to the consumer side. Anything less than that can remain monolithic. MLID speculated that Nvidia might not even care in the near future that their top consumer SKU isn't some >500mm2 honking GPU because their game plan is to just win via software features, not raw horsepower outright. That, along the fact that they much prefer the margins in the enterprise space, means consumers are valued less and less to them moving forward.

Ye I doubt that. Software can only do so much, especially for consumers who mostly just want traditional raw raster and maybe some RT mixed in. I'm not discounting a potential architectural advantage that may allow Nvidia to be more efficient in perf/area, but short of a radical improvement in consumer related software...
And doesn't Nvidia still make a killing from consumer GPUs? I doubt they discontinue their top skus. I agree they will delay chiplets as long as possible, but I don't think MLID is right with what he thinks Nvidia's plan is for consumer GPUs

 

[A///]

Backside power delivery is being tested on Intel 3 before Intel 20A. Idk what they mean by "internal node". Maybe they just have it in labs with no products using it?
I don't think ARL's structure is going to differ from MTL's, nothing like multiple compute tiles or anything imo. Jim thinks there's going to be 3D stacked cache somewhere on it though, but honestly I think if it is there, it's going to be cache on the interposer, which I believe? Intel tried with Ponte Vechio.

It means they're dog fooding their product.

 

[A///]

did anyone confirm that rumor of dlvr making its way to desktop?

 

[Geddagod]

If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.

Ye I agree. This is just conjecture though, I wanted to stress the point that just because Intel is technically capable of using a ton of new stuff in ARL, they might not in order to not risk too much.

 

[Geddagod]

did anyone confirm that rumor of dlvr making its way to desktop?

No. IMO even if it does come, it doesn't look like it's going to help in desktop esp

 

[A///]

No. IMO even if it does come, it doesn't look like it's going to help in desktop esp

Back to the drawing board is what I saw after its abrupt removal for 13th gen.

 

[mikk]

The article you are quoting from agrees that Intel 18A would use High NA if it comes out in time.
The quote you chose from the article doesn't show the full picture- here's some more context

No they don't, you have to read further. To help you out:

While Intel's 18A technology would greatly benefit from High-NA EUV tools, it looks like Intel does not necessarily need Twinscan EXE:5200 machines for this node. Usage of multi-patterning for commercial chips means a longer product cycle, lower productivity, higher risks, and potentially lower yields (though the latter is not cast in stone). Yet, it looks like Intel wants its 18A node to arrive as soon as possible, perhaps because it considers it a major tool that will allow it to recapture process technology leadership from TSMC. Consequently, Intel's updated plans are now to phase in High-NA tooling during 18A's lifecycle if the tools are completed on time.

What you are quoting is the old outdated assumption from 2021 which they repeated. And this is just an assumption from Anandtech, Intel never claimed 18A will be using High-NA. If you can prove that 18A will be using High-NA you should do it but make sure this is a source from Intel, Anandtech is just messy in this regards.

 

[Geddagod]

No they don't, you have to read further. To help you out:




What you are quoting is the old outdated assumption from 2021 which they repeated. And this is just an assumption from Anandtech, Intel never claimed 18A will be using High-NA. If you can prove that 18A will be using High-NA you should do it but make sure this is a source from Intel, Anandtech is just messy in this regards.

I included that quote in my previous comment.
I don't think it's an assumption. This is cited not only by Anandtech, but semiengineering, and many other reporters as well.

Intel 18A products are going to be HVM in 2025. That's from Intel themselves. Clearwater forest, on Intel 18A, perfectly fits that timeline. Do you think Intel is going to have Intel 16A products in HVM in 2025? Because that's the only other node Intel could be talking about for high NA EUV.

Ann claims their nodes have high NA and non-high NA EUV versions in order to safeguard against delays. Now, they not be referencing to Intel 18A like you think. However that doesn't make much sense because this claim was before the announcement that Intel 18A got pushed to 2H 2024. The 2025 node they were almost certainly referencing was Intel 18A.

Ann claims they will put high NA into use as soon as they get the machines up and running, and the only way this makes sense is if Intel 18A was compatible with high NA. Especially when you consider that Ian asked if they could put high NA EUV earlier than expected, Ann still answered yes. So even if she was talking about Intel 16A, it kinda confirms Intel 18A is still compatible since it's the node directly before it

However, maybe I interpreted Ann wrong as well. I'll admit this is very ambiguous and I certainly never try to argue I can't ever be wrong.

 

[mikk]

I included that quote in my previous comment.
I don't think it's an assumption. This is cited not only by Anandtech, but semiengineering, and many other reporters as well.

Then feel free to prove it. Even Anandtech does not believe in it, did you see their updated roadmap? You also keep ignoring the only Intel source where all nodes up to 18A are said to use regular EUV. This is the only Intel source, why do you ignore that? Don't you think the slide would look a bit different if Intel thought High-NA is a realistic option for 18A? You keep arguing with a quote from 2021 while you keep ignoring the newer Intel source from 2022.

From IEDM in late 2022

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk - Semiwiki

Ann Kelleher is Intel’s Executive Vice President, General Manager, Technology Development, and she gave the first plenary talk to kick off the 2022 IEDM, “Celebrating 75 Years of the Transistor A Look at the Evolution of Moore’s Law Innovation”. I am generally not a fan of plenary talks because...

semiwiki.com

Nothing about High-NA. Intel 18A manufacturing ready in H2 2024 does not agree with High-NA. Too late and risky, this is something for a future node after 18A.

 

[igor_kavinski]

MTL first benchmark? https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40985456

 

[Geddagod]

Then feel free to prove it. Even Anandtech does not believe in it, did you see their updated roadmap? You also keep ignoring the only Intel source where all nodes up to 18A are said to use regular EUV. This is the only Intel source, why do you ignore that? Don't you think the slide would look a bit different if Intel thought High-NA is a realistic option for 18A? You keep arguing with a quote from 2021 while you keep ignoring the newer Intel source from 2022.

From IEDM in late 2022

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk - Semiwiki

Ann Kelleher is Intel’s Executive Vice President, General Manager, Technology Development, and she gave the first plenary talk to kick off the 2022 IEDM, “Celebrating 75 Years of the Transistor A Look at the Evolution of Moore’s Law Innovation”. I am generally not a fan of plenary talks because...

semiwiki.com

Nothing about High-NA. Intel 18A manufacturing ready in H2 2024 does not agree with High-NA. Too late and risky, this is something for a future node after 18A.

I literarily just proved it. Unless you think Intel 16A is going to be in HVM in 2025, the only node Intel could be talking about HVM is Intel 18A. This is from your own slide, it says HVM in 2025 for High NA EUV.
Ananadtech DOES believe it. Idk if you read the article you posted but, it literally states

Consequently, Intel's updated plans are now to phase in High-NA tooling during 18A's lifecycle if the tools are completed on time.

I'm not ignoring that source. I'm saying Intel 18A uses BOTH High-NA tooling and regular EUV. Regular EUV is to be used first, and high NA if they get the tools out on time.
This is what Ann implies too, when she says whenever High NA is available they will use it, because their nodes are designed for BOTH High NA and regular EUV.
The slide would not look different, because Intel has been very dodgy on where they will use High NA. Based on their terrible history of node announcements, relatively new work with EUV, and ASML having issues with High NA EUV, I don't think Intel wants to make a specific commitment to the public about where High NA is going to be used. You wonder why Intel keeps on telling us why they will keep on using High NA whenever they can?
Are you just ignoring Ann saying that Intel 18A is developed for both High NA and regular EUV?
Are you just ignoring that this interview was from 2022 not 2021?
Are you just ignoring that if the only evidence I had was from that 2021 article than I wouldn't have been able to say that Intel 18A also had regular EUV designs all the way from my first comment about High NA?

IIRC Intel 18A is also designed for using regular EUV machines too, as a safeguard against delays

And a realistic option for Intel 18A? If anything, High NA EUV would be easier to develop, since they probably would get to avoid more multi-patterning techniques with High NA.
Oh and cmon, literally everything I see online seems to indicate that High NA EUV would be used (even if it's not initially) for Intel 18A. Redfire, semiengineering, TWO different authors on Anandtech.... what I'm suggesting isn't some far off conspiracy theory lmao.
We know Intel has designs for high NA EUV for 18A. We know Intel is going to use high NA EUV for HVM in 2025. We know Intel is going to use high NA EUV as soon as the machine is ready, note, not as soon as the node is ready, since high NA EUV is node agnostic according to Ann herself, and that's crossing paths exactly for when Intel 18A is entering HVM manufacturing- 2025- for Clearwater Forest. That's the proof. Idk why you simply choose to ignore this.

 

[Exist50]

If they remove backside PD from 20A, as a means of derisking, then to me it sounds like they're admitting their schedule was too aggressive. The whole point of that internal Intel 3 node was to get BSPD working.

There's no chance they remove backside PD at this point. Redefining the whole metal stack? You're basically talking about an entirely different node.

 

[A///]

I had a good laugh earlier when I read his post saying "backside PD" not the wisest word combination.

can someone please post a screen shot of this komachukarus twitter so I can see what he said about the igpu on mtl es hitting 2 ghz?

 

[Geddagod]

I had a good laugh earlier when I read his post saying "backside PD" not the wisest word combination.

can someone please post a screen shot of this komachukarus twitter so I can see what he said about the igpu on mtl es hitting 2 ghz?

I don't have access to it either. I heard it from Bionic Squash on the C&C discord server. 2.1Ghz peak actually. You could request access from Komachi's twitter, or DM Bionic Squash ¯\_(ツ)_/¯