Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[IntelUser2000]

But nominal speed is the standard clock being advertised and that associate with the TDP. Even with tile design, the rules apply.

No, with today's designs it's advanced enough that the clocks are workload dependent. Web browsing TDP levels are different from running Intel LinX FPU stress test to tell you of extreme examples. So the clocks would be higher in the former than the latter. It's possible that in some cases like LinX the clock can go slight below TDP clock levels.

That's the whole beauty of Turbo. Maximum performance in all applications.

@SiliconFly You are relying on all the wrong sources.

-The press all believed Meteorlake used TSMC N3 tiles, hence putting out "Intel now using the older N5 node!"
-In fact, Intel never planned for N3, and Meteorlake was always N5.
-Arrowlake changes things.
-Raptorlake refresh was pretty much confirmed by Intel. Day before the original day they were supposed to do a Client roadmap presentation, a roadmap leaked out showing that Raptorlake Refresh is in the cards. Meteorlake is primarily mobile. Raptorlake Refresh gets replaced by Arrowlake, but later than in the year compared to Meteorlake mobile
-If anything, 6+16 for Meteorlake is a rumor. 2+8 and 6+8 are facts.

The Redwood Cove P core in Meteorlake is supposed to be single-digit % faster per clock. Why would you waste time trying to get that out for desktop, if Arrowlake can be accelerated by not releasing Meteorlake desktop?

Intel's primary goals are to get the "5 nodes in 4 years" accomplished. You do that by skipping parts. Skipping Meteorlake to get Arrowlake faster does that goal. Getting Meteorlake out that's barely faster than predecessor does not.

 

[IntelUser2000]

Does a new architecture mean just adding and cutting stuff without changing any principles of how things function, or is function improvements (as branch predictions etc.) necessary for a new architecture?

I believe that resizing, ommiting and adding stuff without changing any function principles may not be that complicated...

Sigh.

@Markfw You don't need to be a CPU designer to know this.

The designers are bound by cost AND space constraints. Within that space they need to arrange the functional blocks in a manner that doesn't waste any space. Or maximizes the amount of features.

Certain blocks will end up being irregular in size.

Now we got that established, think of how the game of Tetris works. You cannot just add to a block without impacting the rest of the block, since the structures are irregular in shape. And not only that, certain blocks need to be in certain proximity to each other. Because that determines performance.

You cannot add or substract a block, or resize it without affecting the rest. And that will affect performance and power characteristics. What you are thinking is not a refresh at all. These people are dealing with HUNDREDS of millions of transistors here. What you are saying will end up a full blown architectural update.

These people are called "architects" for a reason. Think of massive ships like oil tankers. What about Boeing's 787 Dreamliner? What about Skyscrapers over a thousand feet high? Think of those projects, but at a micro-level. That's what CPU architects are.

"Nah just add a floor for a minor update"
"Extra engine for the 787"
"Let's move the propulsion propellers in this oil tanker to a different side"

Take a look at the die shot of Intel's 8086 chip. Then look at 80286, and so on. By the time Pentium rolls in, it goes from being able to almost distinguish individual blocks and wires connecting them, to these array of beautiful solid blocks. If you see how complex the 8086 is with total number of circuitry under 30,000(30 thousand), you'll get an idea of how complex modern CPUs are. Just the core component(which is the most difficult to work with must be in the hundreds of millions now).

Now take that CPU and try modifying it. Knowing fully a SINGLE wire can make it not work at all. Even with aid of computers, it's incredibly difficult.

Literally in a refresh you can change clocks and voltage. Nothing else.

 

[Hulk]

I think it's a decent assumption to make that a 8+16 MTL die could have been planned, even if it never got anywhere. RPL only exists because MTL was coming in late, so that makes it seem like a 8+16 MTL desktop sku would have been planned (or at least an 8+8) to fill out their desktop cadence.
A 6+16 die just sounds weird, because that would just look weird as a successor to Alder Lake desktop, while also looking weird as a successor to Alder Lake mobile as HX skus would on alder lake had 8 big cores. One could argue 6+16 die if Meteor Lake was always planned to be a mobile only lineup, but I don't think so.

After the 10 core Comet Lake, the 8 core Rocket Lake looked weird. But it appeared on the desktop. It's all about what is the best balance of performance and economics for the parts Intel will release. I am under the assumption that the Raptor Refresh will be as fast or faster than a desktop Meteor Lake and cheaper to produce and able to be produced in large numbers.

It's very similar to how the Haswell Refresh (Devil's Canyon) put Broadwell in the mobile box. Or Rocket Lake only appeared because Ice Lake/Tiger Lake clocks weren't where they needed to be for the desktop.

To be completely transparent Raptor Lake is really an Alder Lake Refresh but a really good one as the increased cache, frequency, and cores really pushed Raptor out far ahead of Alder. Problem is I don't see much "gas" in that refresh tank for Alder/Raptor. With clocks at 6GHz, caches quite large, and the core count up to 24, where do they go with it?

As I posted earlier I think we're looking at increased all-core frequencies across the board and call it a day. Just seems like a weak update if that's the case but we'll see.

 

[Exist50]

I think it's a decent assumption to make that a 8+16 MTL die could have been planned, even if it never got anywhere. RPL only exists because MTL was coming in late, so that makes it seem like a 8+16 MTL desktop sku would have been planned (or at least an 8+8) to fill out their desktop cadence.
A 6+16 die just sounds weird, because that would just look weird as a successor to Alder Lake desktop, while also looking weird as a successor to Alder Lake mobile as HX skus would on alder lake had 8 big cores. One could argue 6+16 die if Meteor Lake was always planned to be a mobile only lineup, but I don't think so.

Yeah, 6+16 would be an odd chip, but I don't think it's entirely out of the question that they planned for it at one point. It would sort of make sense as a stopgap for Arrow Lake a bit earlier, and as an option for high end mobile. But that's pretty weak positioning all said. I think the lack of a compelling gaming advantage would hurt the most. And given Intel's pretty drastic cost cutting, makes sense if it were canceled.

 

[Geddagod]

Yeah, 6+16 would be an odd chip, but I don't think it's entirely out of the question that they planned for it at one point. It would sort of make sense as a stopgap for Arrow Lake a bit earlier, and as an option for high end mobile. But that's pretty weak positioning all said. I think the lack of a compelling gaming advantage would hurt the most. And given Intel's pretty drastic cost cutting, makes sense if it were canceled.

I would believe they planned it, but it would make much more sense if the die planned was 8+16, and they just thought they could hit the yield requirements or something, and just decided to disable 2 of those cores because of it. So essentially a 6+16 without having to redesign an entire die.

 

[Geddagod]

After the 10 core Comet Lake, the 8 core Rocket Lake looked weird. But it appeared on the desktop. It's all about what is the best balance of performance and economics for the parts Intel will release. I am under the assumption that the Raptor Refresh will be as fast or faster than a desktop Meteor Lake and cheaper to produce and able to be produced in large numbers.

It's very similar to how the Haswell Refresh (Devil's Canyon) put Broadwell in the mobile box. Or Rocket Lake only appeared because Ice Lake/Tiger Lake clocks weren't where they needed to be for the desktop.

To be completely transparent Raptor Lake is really an Alder Lake Refresh but a really good one as the increased cache, frequency, and cores really pushed Raptor out far ahead of Alder. Problem is I don't see much "gas" in that refresh tank for Alder/Raptor. With clocks at 6GHz, caches quite large, and the core count up to 24, where do they go with it?

As I posted earlier I think we're looking at increased all-core frequencies across the board and call it a day. Just seems like a weak update if that's the case but we'll see.

8 core RKL was a diff situation. The cores were physically too big. What are the chances that Intel thought yields would just be bad enough to have to cancel the 8+16 die, but just good enough that they would be able to only have to disable 2 P-cores? And even if that were true, what are the chances Intel decided to commit to redesigning the entire die off that premise?
I agree with RPL-R running out of gas. The Intel copium in me is hoping we see the rumored increased L3 caches in RPL cores of EMR into desktop, but realistically I know that's almost certainly not going to happen... LOL

 

[A///]

Even Intel wanted to forget launching rocketlake.

 

[Hulk]

8 core RKL was a diff situation. The cores were physically too big. What are the chances that Intel thought yields would just be bad enough to have to cancel the 8+16 die, but just good enough that they would be able to only have to disable 2 P-cores?

We don't know that ML desktop was cancelled because of yields, or limited clock speed, or it was always supposed to be mobile only or some other reasons or combination of reasons.

Based on Intel node history I am under the assumption that it's not only yields affecting ML desktop but more frequency scaling. I believe that Intel 4 is hitting acceptable clocks for mobile with good efficiency, but up against Raptor Lake, which hit's 6GHz it's simply not enough to be competitive with that part on the desktop.

You are right in that the interesting thing about this is if ML was initially planned as 8+16 and frequency scaling and/or yields are preventing it from hitting the desktop then perhaps Intel is fusing off cores to make it 6+16 or whatever they need.

Ultimately I think the simplest explanation is the most accurate. I think ML was supposed to be 6+16 with 15% better IPC from the Coves and as much or more IPC improvement from the Monts. Assuming equal clocks to RL this would put the P's as a package down about 10% from RL. But, and this is important ST performance would be better than RL, actually 15% better up to 6 cores, which is all most applications use that can't "dig" into the E's.

So if clocks are on par with RL for applications like gaming, video, and photo editing ML would bench faster than RL. And the E's would be 15% more performant than the RL E's. Further assuming P's and E's each represent about half of total MT performance in an app like Cinebench, then this theoretical ML clocking near RL levels could be faster in mainstream applications only hitting 6 cores hard and in highly MT applications.

For this to happen Intel 4 clocks on ML would have to be in the 5.4 to 5.5 range and perhaps Intel was hoping they'd get there but knew if they didn't RL would still be useful as a mobile only release.

If ES parts are hitting 4GHz then that's over 1GHz from where they need to be. Even 5GHz might not be enough to beat RL so Intel pulled back on the ML desktop release and went with their "plan B," which was ready to go all along. Mobile ML.

I don't see how they could have gotten here any other way as these giant companies don't change direction easily. Then again I'm extrapolating on a lot of rumors, which is never a reliable way to make predictions.

 

[Hulk]

Even Intel wanted to forget launching rocketlake.

I wish I had started a website just to review Rocket Lake and title the review

"Rocket Lake: Failure to Launch"

Or

"Rocket Lake" Misses Orbit and Splashes Down"

 

[Geddagod]

We don't know that ML desktop was cancelled because of yields, or limited clock speed, or it was always supposed to be mobile only or some other reasons or combination of reasons.

Based on Intel node history I am under the assumption that it's not only yields affecting ML desktop but more frequency scaling. I believe that Intel 4 is hitting acceptable clocks for mobile with good efficiency, but up against Raptor Lake, which hit's 6GHz it's simply not enough to be competitive with that part on the desktop.

You are right in that the interesting thing about this is if ML was initially planned as 8+16 and frequency scaling and/or yields are preventing it from hitting the desktop then perhaps Intel is fusing off cores to make it 6+16 or whatever they need.

Ultimately I think the simplest explanation is the most accurate. I think ML was supposed to be 6+16 with 15% better IPC from the Coves and as much or more IPC improvement from the Monts. Assuming equal clocks to RL this would put the P's as a package down about 10% from RL. But, and this is important ST performance would be better than RL, actually 15% better up to 6 cores, which is all most applications use that can't "dig" into the E's.

So if clocks are on par with RL for applications like gaming, video, and photo editing ML would bench faster than RL. And the E's would be 15% more performant than the RL E's. Further assuming P's and E's each represent about half of total MT performance in an app like Cinebench, then this theoretical ML clocking near RL levels could be faster in mainstream applications only hitting 6 cores hard and in highly MT applications.

For this to happen Intel 4 clocks on ML would have to be in the 5.4 to 5.5 range and perhaps Intel was hoping they'd get there but knew if they didn't RL would still be useful as a mobile only release.

If ES parts are hitting 4GHz then that's over 1GHz from where they need to be. Even 5GHz might not be enough to beat RL so Intel pulled back on the ML desktop release and went with their "plan B," which was ready to go all along. Mobile ML.

I don't see how they could have gotten here any other way as these giant companies don't change direction easily. Then again I'm extrapolating on a lot of rumors, which is never a reliable way to make predictions.

We know RPL was never supposed to exist, and only exists because MTL got delayed. It makes sense that MTL would have had both desktop and mobile, especially since Intel doesn't usually launch mobile only if their nodes are working right.
MTL also is a die shrink architecture. Initial die shrink architectures are always just straight up die shrinks of the previous architecture. Cannon Lake, Ivy Bridge, etc etc all follow it. Low IPC gains.
If IPC was originally supposed to be higher, than the IPC would have been higher. I heard that they estimate IPC in design goals, but jumping from ~15% to low single digits just doesn't make sense. Low single digits is a die shrink, ~15% is a GLC level revamp.
I could see an argument that maybe MTL was originally supposed to be 8+8 following ADL, but 6+16 just sounds too weird.
Also who came up with the 6+16 rumor again? I'm curious.

 

[Geddagod]

I wish I had started a website just to review Rocket Lake and title the review

"Rocket Lake: Failure to Launch"

Or

"Rocket Lake" Misses Orbit and Splashes Down"

I would love to pick up some old hardware for cheap and just start looking into answers for questions that people just don't go over in reviews and stuff.
Like PPC scaling for GLC vs RPL vs Zen 4
Mesh vs ringbus latency and effect on gaming
Just a comprehensive list of PPC in multiple applications over the past couple generations
RPL vs GLC efficiency (how much does L2 cache help?)
Palm Cove IPC
Tiger Lake 11980HK, on those chinese motherboads, overclocked
Cypress Cove vs Sunny Cove vs Willow Cove energy + frequency scaling
A bunch of other stuff too. Alas maybe someday :c

 

[coercitiv]

I wish I had started a website just to review Rocket Lake and title the review

You need a seasoned snarky writer for the job:
"Rocket Lake: too big, too fail."

 

[DrMrLordX]

TSMC capacity is meant for the AXG group (N3/N5/N6). Whereas 20A is for the client group (more specifically Arrow Lake).

That assumes 20a is healthy enough for desktop parts (or really, anything). Intel may be forced to use N3 for more than just GPU tiles.

 

[IntelUser2000]

@Hulk According to reliable sources, Meteorlake is single digit % gains. Raichu is joking that it may even be 1%. 15% is MLID, and maybe even RGT level nonsense. 15% is a drastic architectural change and improvement.

#dontforget29%Zen4

Obviously if it wasn't delayed Meteorlake would have been coming to desktop. But you are talking them releasing it instead of Raptorlake. Raptorlake wasn't supposed to exist. It was supposed to be Alder/Meteor not Alder/Raptor.

Also based on leaks and rumors, a 14900K that's 3-5% faster but say 30% lower power is very mediocre. It needs Arrowlake to face Zen 5 period. They did something really good with Raptorlake despite the issues. You don't want to lose that momentum.

Sure, a refresh of an emergency part does not look good. However, it accelerates the big picture, which is not delaying process technology.

Also who came up with the 6+16 rumor again? I'm curious.

It's not a rumor. It was in planning. It was leaked several months ago. And according to that leak it's

-High End Desktop: 8+16 Arrowlake
-Low/Medium Desktop: 6+16 Meteorlake

That's a difficult thing differentiating between rumors and leaks. Just the sheer amount of garbage on the internet doesn't help either. What/where/when to look for all matter.

 

[Geddagod]

@Hulk According to reliable sources, Meteorlake is single digit % gains. Raichu is joking that it may even be 1%. 15% is MLID, and maybe even RGT level nonsense. 15% is a drastic architectural change and improvement.

#dontforget29%Zen4

Obviously if it wasn't delayed Meteorlake would have been coming to desktop. But you are talking them releasing it instead of Raptorlake. Raptorlake wasn't supposed to exist. It was supposed to be Alder/Meteor not Alder/Raptor.

Also based on leaks and rumors, a 14900K that's 3-5% faster but say 30% lower power is very mediocre. It needs Arrowlake to face Zen 5 period. They did something really good with Raptorlake despite the issues. You don't want to lose that momentum.



It's not a rumor. It was in planning. It was leaked several months ago. That's a difficult thing differentiating between rumors and leaks. Just the sheer amount of garbage on the internet doesn't help either. What/where/when to look for all matter.

Ok fine, where was the leak from?

 

[IntelUser2000]

You need a seasoned snarky writer for the job:
"Rocket Lake: too big, too fail."

That's awesome haha!

 

[SiliconFly]

We know RPL was never supposed to exist, and only exists because MTL got delayed. It makes sense that MTL would have had both desktop and mobile, especially since Intel doesn't usually launch mobile only if their nodes are working right.
MTL also is a die shrink architecture. Initial die shrink architectures are always just straight up die shrinks of the previous architecture. Cannon Lake, Ivy Bridge, etc etc all follow it. Low IPC gains.
If IPC was originally supposed to be higher, than the IPC would have been higher. I heard that they estimate IPC in design goals, but jumping from ~15% to low single digits just doesn't make sense. Low single digits is a die shrink, ~15% is a GLC level revamp.
I could see an argument that maybe MTL was originally supposed to be 8+8 following ADL, but 6+16 just sounds too weird.
Also who came up with the 6+16 rumor again? I'm curious.

Intel has already launched mobile only with Tiger Lake in 2020. It wasn't exceptional and it wasn't bad either.

 

[Geddagod]

Intel has already launched mobile only with Tiger Lake in 2020. It wasn't exceptional and it wasn't bad either.

Yup. But they only launched that as mobile only because 10nm was still not ready at that point . IIRC Tiger Lake launched as 4 core parts first and then 8 core parts, and never had exceptional volume until a while after launch too.

 

[SiliconFly]

Yup. But they only launched that as mobile only because 10nm was still not ready at that point . IIRC Tiger Lake launched as 4 core parts first and then 8 core parts, and never had exceptional volume until a while after launch too.

Same might be happening with Intel 4 is my guess.

Maybe thats the reason they're stuck with MTL 6+8

 

[SiliconFly]

That assumes 20a is healthy enough for desktop parts (or really, anything). Intel may be forced to use N3 for more than just GPU tiles.

Has nothing to do with node health. It's impossible to change nodes so late in the cycle. If they wanted the ARL cpu tile to be in TSMC N3, they would have started the design back in 2021/2022 itself. But Intel clearly mentioned ARL cpu is only Intel 20A then. No one (including Intel itself) never ever mentioned that they're working on a TSMC N3 ARL cpu. And it can't happen anymore because it's too late. No time left. It has to be 20A or no ARL!

 

[msj10]

Ok fine, where was the leak from?

it was by someone on twitter who posted these slides but later deleted them

 

[BorisTheBlade82]

Yeah, 6+16 would be an odd chip, but I don't think it's entirely out of the question that they planned for it at one point. It would sort of make sense as a stopgap for Arrow Lake a bit earlier, and as an option for high end mobile. But that's pretty weak positioning all said. I think the lack of a compelling gaming advantage would hurt the most. And given Intel's pretty drastic cost cutting, makes sense if it were canceled.

Well, my line of thinking is, that when they decided for only 6P cores, they assumed them to be much more powerful than their predecessors and competition. But from what we hear, this was just a miserable failure.

 

[SiliconFly]

it was by someone on twitter who posted these slides but later deleted them

View attachment 78025View attachment 78026

It's hard to cite this as evidence considering the source is not easily traceable. But the same time, it's also never a good idea to say MTL 6+16 is fake cos there are no good leaks about them. Your info maybe true. Or maybe not. No one know yet. Gotta wait and watch.

 

[SiliconFly]

Well, my line of thinking is, that when they decided for only 6P cores, they assumed them to be much more powerful than their predecessors and competition. But from what we hear, this was just a miserable failure.

Actually no. MTL's Redwood Cove can be upto 20% faster than RPL's Raptor Cove at the same power due to node jump. It's waaaay superior.

 

[eek2121]

Wait a minute. Wasn't the rumor that Meteor Lake would be mobile only because Intel couldn't get frequencies to ramp up on the new node? If TMSC is doing the CPU tiles then what's the deal with the node? It's not even Intel's node?

That was most certainly just speculation, especially as mobile parts are also high frequency parts.

Intel will likely be using MTL to ramp up production of their new node. Because of this capacity will be limited at first.

No it wasn't, there is no serious rumor like that. Some people may speculate this is the reason but this is just a guess. Also there is no confirmation about no MTL for desktop.

6+8 was confirmed on an official Intel slide at one point IIRC. Not a leaked one either.

Meteor Lake coming to desktop is actually a pretty safe bet. The question is when, and in what capacity. Tiger Lake came to desktop, but not in the form of a regular release. One of the reasons I suspect Intel won't bring it to desktop for something like an i7 part is because it would look way better than the corresponding Raptor Lake Refresh i9 part in terms of power consumption. The other big one I mentioned above: Capacity. Intel has to be able to sell millions of these things to OEMs. What I think we will see first is (purely my speculation based on data Intel has provided):

Desktop: Raptor Lake Refresh
Laptop: A mix of Raptor Lake Refresh chips and Meteor Lake chips, with MTL-S likely targeting ultrabooks and other low power devices.

Next year, after Arrow Lake drops, we'll see MTL-S make it's way to desktop in some form of fashion, likely in a NUC or similar device. I suspect the mainstream core series will be Arrow Lake, however. They COULD mix it up (they kinda did with ADL-S and RPL-S), but there is really no benefit to doing so.