Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Exist50]

View attachment 77825View attachment 77826

Above slides seem indicating Die2Die power delivery from SoC, is it?

I think I see the confusion. The top slide is referring to the location of die-to-die interfaces for communication between the active (top) chiplets. The bottom, as mentioned in the upper right, is basically a cross section of the base die. That big pillar (TSV) in the center is where the power would come from. The metal layers at the top are where the signals are routed between dies, and possibly some second order fanout for power delivery. But there should be no power delivered between the top dies.

 

[uzzi38]

Below is my understanding of upcoming Meteor Lake and Arrow Lake CPU and I am trying to calculate how much power needed in TDP term.

	13th RPL-H	MTL-H	ARL-HX
Release Date	Q1 2023	Q1 2024?	Q1 2025?
Process Node	Intel 7	Intel 4 + N5 + N6	Intel 20A + N5 + N6
CPU Max Cores	6P + 8E	6P + 8E	8E + 16E
L3 Caches	24MB	24MB	36MB
P Core Base Clock	2.6 GHz	?	?
P Core Turbo Clock	5.4 GHz	?	?
iGPU	96 EU - 1.5GHz	GT2 Xe LPG 64EU - ?	GT2 Xe LPG 64EU - ?
TDP	45 W	45 W	55 W
Max Turbo Power	115 W	?	?
CPU Tile	NA	25 W	35 W
SoC + IOE Tiles (est)	NA	10 W	10 W
GPU Tile (est)	NA	10 W	10 W
Power per CPU core (4E ~ 1P)		3.13 W	2.92 W

• As far as I understand, SoC tile is the one receiving power from the socket then distribute to other tiles (namely CPU, GPU and IOE) through die to die connectors. That's why I figure SoC tile consume much more power than conventional PCH. For simplification, I combine SoC and IOE tiles as total power of 10W.
• GPU tiles are based on Alchemist graphics engine; so I calculate upon A370M's TGP of 35W. With half of Xe cores and newer process, 10W seems reasonable?
• That left 25W for CPU tile; here comes the interesting part cause this is Intel's first CPU that based on EUV lithography and I am expecting higher clock speed. For reference, AMD's Phoenix has TDP of 35W with base clock speed of 4 GHz and 2.8GHz iGPU speed which are rather impressive. Power per core figures might be good indicator of process advancement in the future cause AMD and Intel are moving to chiplet/tile design...

CPU, GPU, SoC tiles etc would surely be dynamic in their power usage rather than a set 25W/10W/10W split. You shouldn't be seeing the GPU tile pull or reserve 10W for non-GPU accelerated tasks.

Hopefully.

 

[Tigerick]

CPU, GPU, SoC tiles etc would surely be dynamic in their power usage rather than a set 25W/10W/10W split. You shouldn't be seeing the GPU tile pull or reserve 10W for non-GPU accelerated tasks.

Hopefully.

Sure, the clock of all tiles would be dynamic but the base of operations will be set by certain power criteria, hence TDP. When Intel advertise all cores base clock of CPU like 2.5GHz, that is nominal speed at TDP of said 45W. With turbo mode, the CPU speed will go much higher. With Speedster, CPU speed would go much lower. But nominal speed is the standard clock being advertised and that associate with the TDP. Even with tile design, the rules apply.

 

[Tigerick]

I think I see the confusion. The top slide is referring to the location of die-to-die interfaces for communication between the active (top) chiplets. The bottom, as mentioned in the upper right, is basically a cross section of the base die. That big pillar (TSV) in the center is where the power would come from. The metal layers at the top are where the signals are routed between dies, and possibly some second order fanout for power delivery. But there should be no power delivered between the top dies.

Hmm, come to think of SoC design with 3 die2die connectors are really stressing the CPU. SoC has to coordinate CPU, GPU, memory controllers and then output the video through IOE which has power of it own. No wonder Intel has to put ULV Atom within SoC...

 

[SiliconFly]

Below is my understanding of upcoming Meteor Lake and Arrow Lake CPU and I am trying to calculate how much power needed in TDP term.

	13th RPL-H	MTL-H	ARL-HX
Release Date	Q1 2023	Q1 2024?	Q1 2025?
Process Node	Intel 7	Intel 4 + N5 + N6	Intel 20A + N5 + N6
CPU Max Cores	6P + 8E	6P + 8E	8E + 16E
L3 Caches	24MB	24MB	36MB
P Core Base Clock	2.6 GHz	?	?
P Core Turbo Clock	5.4 GHz	?	?
iGPU	96 EU - 1.5GHz	GT2 Xe LPG 64EU - ?	GT2 Xe LPG 64EU - ?
TDP	45 W	45 W	55 W
Max Turbo Power	115 W	?	?
CPU Tile	NA	25 W	35 W
SoC + IOE Tiles (est)	NA	10 W	10 W
GPU Tile (est)	NA	10 W	10 W
Power per CPU core (4E ~ 1P)		3.13 W	2.92 W

• As far as I understand, SoC tile is the one receiving power from the socket then distribute to other tiles (namely CPU, GPU and IOE) through die to die connectors. That's why I figure SoC tile consume much more power than conventional PCH. For simplification, I combine SoC and IOE tiles as total power of 10W.
• GPU tiles are based on Alchemist graphics engine; so I calculate upon A370M's TGP of 35W. With half of Xe cores and newer process, 10W seems reasonable?
• That left 25W for CPU tile; here comes the interesting part cause this is Intel's first CPU that based on EUV lithography and I am expecting higher clock speed. For reference, AMD's Phoenix has TDP of 35W with base clock speed of 4 GHz and 2.8GHz iGPU speed which are rather impressive. Power per core figures might be good indicator of process advancement in the future cause AMD and Intel are moving to chiplet/tile design...

MTL is expected Q4 this year.

MTL Xe1 tGPU is rumored to be TSMC N5. But Intel hasn't confirmed that yet i think. Their ARL tGPU which is also Xe1 but many a times it was mentioned it's going to be on N3. Considering, Intel already has a lot of N3 capacity now & it's a waste of time and resources to just port the same design to yet another node, it's very much possible both the tGPUs might actually end up being N3. Or N5. We don't know for sure. Gotta wait for more info.

The core count for MTL isn't confirmed yet. Many say it's 6+8. And many say it's 6+16. The latter makes more sense. 6+8 won't cut it anymore as it's a huge step backward. Intel might shoot itself in the foot with 6+8. I think it's gonna be 6+16.

Due to the density increase because of node jump, there is always a possibility MTL might get more L3 cache than RPL. 30MB sounds about right? Not sure though.

45W TDP parts confirmed. But 55W parts not ruled out yet. Got to wait for further announcements. Might happen as they need a replacement for their HX series.

 

[jpiniero]

6+8 won't cut it anymore as it's a huge step backward.

6+8 is what the P maxes out now, so not really. There's also a 2+8 die.

Given that desktop is getting Raptor Lake Refresh, I imagine there will be HX of that at the very least too.

 

[SiliconFly]

6P is pretty much solid info. But why do you think 16E isn't possible? It's not confirmed yet. Even 8E isn't confirmed yet.

 

[Exist50]

MTL Xe2 tGPU is rumored to be TSMC N5. But Intel hasn't confirmed that yet i think. Their ARL tGPU which is also Xe2 but many a times it was mentioned it's going to be on N3.

Without commenting on the rest, MTL's GPU is Alchemist-based, not Battlemage/Xe2.

 

[Hulk]

Wait a minute. Wasn't the rumor that Meteor Lake would be mobile only because Intel couldn't get frequencies to ramp up on the new node? If TMSC is doing the CPU tiles then what's the deal with the node? It's not even Intel's node?

 

[mikk]

Wait a minute. Wasn't the rumor that Meteor Lake would be mobile only because Intel couldn't get frequencies to ramp up on the new node? If TMSC is doing the CPU tiles then what's the deal with the node? It's not even Intel's node?

No it wasn't, there is no serious rumor like that. Some people may speculate this is the reason but this is just a guess. Also there is no confirmation about no MTL for desktop.

 

[Exist50]

Wait a minute. Wasn't the rumor that Meteor Lake would be mobile only because Intel couldn't get frequencies to ramp up on the new node? If TMSC is doing the CPU tiles then what's the deal with the node? It's not even Intel's node?

TSMC is not doing the Meteor Lake CPU tile. They're doing all the other top dies though.

 

[SiliconFly]

Without commenting on the rest, MTL's GPU is Alchemist-based, not Battlemage/Xe2.

Opps. My bad. Updating...

 

[SiliconFly]

Wait a minute. Wasn't the rumor that Meteor Lake would be mobile only because Intel couldn't get frequencies to ramp up on the new node? If TMSC is doing the CPU tiles then what's the deal with the node? It's not even Intel's node?

Just rumors. Waiting for more info. At this point we can easily rule out 6+8 as it appears to be a sandbagging trick. If I remember right, Intel 4 HP libraries should be able to handle 5.5 GHz easily. Beyond that is we still don't yet.

 

[BorisTheBlade82]

Just rumors. Waiting for more info. At this point we can easily rule out 6+8 as it appears to be a sandbagging trick. If I remember right, Intel 4 HP libraries should be able to handle 5.5 GHz easily. Beyond that is we still don't yet.

IIRC the "big" MTL compute tile is supposed to have gotten cancelled. IMHO that is the 6/8+16 you are talking about. Now only the 6+8 as well as the 2+8 are left. That might arrive in the Mid to Low range Desktop at some point but should start as mobile only.
MTL looks like IceLake-U at best and Cannon Lake at worst.

 

[jpiniero]

Way I'd interpret is that the 24/25 desktop would be Arrow Lake (at TSMC) for the high end and the 6+8 Meteor Lake tile at the lower end.

 

[DrMrLordX]

Way I'd interpret is that the 24/25 desktop would be Arrow Lake (at TSMC) for the high end and the 6+8 Meteor Lake tile at the lower end.

Wasn't someone saying that Intel would be using TSMC N3 for desktop parts and 20a for mobile parts in late 2024?

 

[SiliconFly]

Wasn't someone saying that Intel would be using TSMC N3 for desktop parts and 20a for mobile parts in late 2024?

TSMC capacity is meant for the AXG group (N3/N5/N6). Whereas 20A is for the client group (more specifically Arrow Lake).

 

[SiliconFly]

Way I'd interpret is that the 24/25 desktop would be Arrow Lake (at TSMC) for the high end and the 6+8 Meteor Lake tile at the lower end.

Actually, intel's plan for desktop parts hasn't leaked yet. Some rumors say meteor lake has no desktop parts! Doesn't sound right.

Meteor lake is a Q4 2023 product.
Arrow Lake is Q3 2024 product.

Intel going without any new desktop parts from late this year to Q3 2024 doesn't sound right. Even a raptor lake refresh doesn't sound very appealing. I'm sure they're cooking something better than a RPL refresh. Wish they shed some light sooner rather than later.

 

[BorisTheBlade82]

Actually, intel's plan for desktop parts hasn't leaked yet. Some rumors say meteor lake has no desktop parts! Doesn't sound right.

Meteor lake is a Q4 2023 product.
Arrow Lake is Q3 2024 product.

Intel going without any new desktop parts from late this year to Q3 2024 doesn't sound right. Even a raptor lake refresh doesn't sound very appealing. I'm sure they're cooking something better than a RPL refresh. Wish they shed some light sooner rather than later.

I fear, that exactly what you fear is what will happen 🤷🏽‍♂️

 

[jpiniero]

Actually, intel's plan for desktop parts hasn't leaked yet. Some rumors say meteor lake has no desktop parts! Doesn't sound right.

There was a legit looking roadmap leaked which had Raptor Lake Refresh on it. If anything, the question is going to be whether Intel feels compelled to also do mobile rebrands to help cover up Meteor Lake's low supply.

 

[Kepler_L2]

There was a legit looking roadmap leaked which had Raptor Lake Refresh on it. If anything, the question is going to be whether Intel feels compelled to also do mobile rebrands to help cover up Meteor Lake's low supply.

That will be the case yep. It's basically Ice Lake/Comet Lake generation all over again.

 

[Exist50]

That will be the case yep. It's basically Ice Lake/Comet Lake generation all over again.

Seems more like Tiger Lake. 6+8 should be enough for use in the H series. So just like Tiger Lake, we're going to get mobile on the new gen, and desktop on the older. Though I guess unlike Tiger Lake, we should eventually see MTL in the mainstream to low end desktop market.

 

[SiliconFly]

Seems more like Tiger Lake. 6+8 should be enough for use in the H series. So just like Tiger Lake, we're going to get mobile on the new gen, and desktop on the older. Though I guess unlike Tiger Lake, we should eventually see MTL in the mainstream to low end desktop market.

MTL 6+8 is just a rumor. Another rumor said 6+16. The later sounds more plausible.

 

[Exist50]

MTL 6+8 is just a rumor. Another rumor said 6+16. The later sounds more plausible.

Intel themselves have shown a 6+8 die. It's the only one we have confirmation for other than 2+8.

 

[Geddagod]

Intel themselves have shown a 6+8 die. It's the only one we have confirmation for other than 2+8.

I think it's a decent assumption to make that a 8+16 MTL die could have been planned, even if it never got anywhere. RPL only exists because MTL was coming in late, so that makes it seem like a 8+16 MTL desktop sku would have been planned (or at least an 8+8) to fill out their desktop cadence.
A 6+16 die just sounds weird, because that would just look weird as a successor to Alder Lake desktop, while also looking weird as a successor to Alder Lake mobile as HX skus would on alder lake had 8 big cores. One could argue 6+16 die if Meteor Lake was always planned to be a mobile only lineup, but I don't think so.