Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[511]

Some Japanese leaker is leaking Intel stuff feel free to check him out

https://twitter.com/x/status/1882692883062686163

 

[SiliconFly]

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[igor_kavinski]

Thank god Itanium failed. Otherwise, all x86 processors would still be Quad core.

I think HP is cursed. They were going to revolutionize the future of computing with the memristor. So much hype.

HP bets it all on The Machine, a new computer architecture based on memristors and silicon photonics

HP, one of the original 800lb Silicon Valley gorillas that has seen much happier days, is staking everything on a brand new computer architecture that it calls... The Machine. Judging by an early report from Bloomberg Businessweek, up to 75% of HP's once fairly illustrious R&D division -- HP...

www.extremetech.com

Andddddd NOTHING. Not a single memristor in any device on the market. Big or small.

 

[del42sa]

https://www.tomshardware.com/pc-com...-samples-intended-for-validation-and-research

Intel's Nova Lake chips are currently undergoing validation

 

[SiliconFly]

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[511]

Are we going to get increase in core count sizes with Nova like we can get 8+24 ?

 

[igor_kavinski]

Are we going to get increase in core count sizes with Nova like we can get 8+24 ?

I would prefer they make it 16+8. Eight weak cores are enough for background stuff.

 

[SiliconFly]

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[OneEng2]

Intel's cooking something very interesting. The fact they've foregone desktop next year and committed all resources to NVL says they're working hard on it. Nova Lake is the first true All Pat design. And it should be very interesting. I'm guessing it's a major departure from LNC.

I suspect it is a tweaked ARL. Maybe most seriously tweaked in the memory and latency portion of the architecture.

I wouldn't expect too much improvement over LNL single core in most situations, but a hearty improvement over ARL H in laptop.... Which is more important for Intel anyway.

Mostly, they need to get their cost and latency down. I bet this does the trick.
More important is the impact on CWF IMO. NVL will be out first glimpse into what might be possible for a high core next generation Intel DC processor.

 

[511]

I would prefer they make it 16+8. Eight weak cores are enough for background stuff.

E cores will have same IPC as P cores by Nova Lake and full ISA compatibility if i were to guess each E core will be as powerful as a 13900K P core at 5.8Ghz

 

[igor_kavinski]

E cores will have same IPC as P cores by Nova Lake and full ISA compatibility if i were to guess each E core will be as powerful as a 13900K P core at 5.8Ghz

Why have a P-core then? Just give it 2 P-cores and 32 E-cores.

 

[Magio]

Why have a P-core then? Just give it 2 P-cores and 32 E-cores.

Same IPC doesn't necessarily mean same performance. For example, Skymont is already quite close to Lion Cove in IPC, but it doesn't clock anywhere near as high so it ends up a long way off in pure performance.

Even if that is probably the eventual goal (and Arctic Wolf is the first step in that direction), it will take at least a few generational enhancements for the E-core to start trampling on the P-core's turf, and until then you'll still need a bunch of P-cores.

 

[igor_kavinski]

until then you'll still need a bunch of P-cores.

OK, I will allow max 4 P-cores + 32 E-cores

 

[MarkizSchnitzel]

I don't get this talk of E-core vs P-core, and E-core getting closer in performance..

Whichever core has the highest performance is a P-core.
If they develop Skymont strain so that it matches Lion Cove P-core in performance, but at better efficiency, it just becomes a better more efficient P-core, right?

But they will then also need/want a new low power even higher efficiency e-core for low end tasks?

It seems like they are only pushing Skymont because Lion Cove is not very good and they need MT performance.
If Lion Cove was better, they could instead focus on getting Skymont more EFFICIENT, instead of more performant.

 

[OneEng2]

E cores will have same IPC as P cores by Nova Lake and full ISA compatibility if i were to guess each E core will be as powerful as a 13900K P core at 5.8Ghz

I disagree.

As mentioned, there is the matter of clock speed, there is also the matter of performance in WHAT workload?

At the end of the day, raising clock speed on a transistor raises power greatly (and transistor design changes). Keeping performance high is often more about how many threads you can keep busy and full, which is more about SMT and low latency cache design that strict IPC measurements.

I don't disagree with the P Core and E Core design strategy, but I do question Intel's use of totally different cores to achieve this vs AMD's approach of utilizing the same core design with transistor and cache modifications.

Time will tell which approach wins out.

 

[SiliconFly]

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[OneEng2]

Yep. Arctic Wolf E core at max clocks should have similar performance to RPL P core at max clocks. But it should be a tad bigger than Sykmont.


NVL P core is expected to have higher performance.

Seems like a bit of a stretch to be predicting Arctic Wolf E core performance at this time. Also, comparisons to RPL P core also seem a bit off base.

How will AW E Core compare to the Cove core of that time window ..... or Zen 6 C .... and in what workloads.

I do agree that the current "Cove" performance APPEARS to be lackluster from a PPA standpoint compared to Zen 5 (as an example); however, the current Cove is suffering from insane latency issues to its L3 cache and ring bus.

Everyone seems to believe that Intel is filled with dottering morons that are allowed to run amok with their designs in some kind of cult like tunnel within the company. I am relatively sure the design engineers were told to get the compute tile size down for cost and yield concerns, and that the time they had to do it in left a few latency holes that are crippling the core.

I personally think (here is a counter prediction) that it is more likely that Cove will become the backbone single unifying architecture and that "mont" will go away .

Now .... stick that in your pipe and smoke it .

FWIW, you could all be correct and Cove may be so totally flawed that it can not be saved.

 

[SiliconFly]

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[igor_kavinski]

I personally think (here is a counter prediction) that it is more likely that Cove will become the backbone single unifying architecture and that "mont" will go away .

May be possible if they do something like an E-core within a P-core where the high performance parts of the core only wake up during strenuous workloads and the benefit would be in terms of context switch latency and shared cache (thus saving die area for separate caches) to move the thread onto the P-core structures for high speed processing.

 

[igor_kavinski]

I'm hoping Pat has done a good job with NVL.

He didn't do anything other than sit in on 15 minute PPT presentations and trying hard not to fall asleep. Had he even an iota of credit in any core's designs, he would surely be telling the world about it.

 

[SiliconFly]

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[cannedlake240]

Seems like a bit of a stretch to be predicting Arctic Wolf E core performance at this time. Also, comparisons to RPL P core also seem a bit off base.

How will AW E Core compare to the Cove core of that time window ..... or Zen 6 C .... and in what workloads.

I do agree that the current "Cove" performance APPEARS to be lackluster from a PPA standpoint compared to Zen 5 (as an example); however, the current Cove is suffering from insane latency issues to its L3 cache and ring bus.

Everyone seems to believe that Intel is filled with dottering morons that are allowed to run amok with their designs in some kind of cult like tunnel within the company. I am relatively sure the design engineers were told to get the compute tile size down for cost and yield concerns, and that the time they had to do it in left a few latency holes that are crippling the core.

I personally think (here is a counter prediction) that it is more likely that Cove will become the backbone single unifying architecture and that "mont" will go away .

Now .... stick that in your pipe and smoke it .

FWIW, you could all be correct and Cove may be so totally flawed that it can not be saved.

What's wrong with monts lol, ISA/avx512? That's solvable, especially if they redesign it as a full fledged P core. Lack of SMT? New Coves don't have it either. Arrow is not the only implementation of the P core. Lunar lake has the fixed version without latency problems, yet still lags Apple, QC Oryon 2, arm x925 on a similar node.

 

[igor_kavinski]

As a past lead architect, he knows a thing or two about CPUs.

Correction: knew

Now he's just a very expensive stage dancer.

 

[SiliconFly]

.

 

[Thunder 57]

Like Lisa?

Last I checked Lisa was still CEO.