Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[dullard]

The average is low because Blender has several cycles, at the start it is idling for 15s and then it goes at full throughput for 3 phases with some interrupts, the 275W are the phases of full throughput, that s not just short peaks as you seems to believe.

For the rest there will be reviews in less than two moths, and we ll surely have some leaks in the meantime, so we ll see how things pan out in the next weeks or so.

So now you ignore point #1 and #2. Okay Abwx, you do you. Changing the goalpost and posting conflicting information isn't making your case though.

Up to 10 ms is the limit of time for power spikes above PL2 unless Computerbase had malfunctioning equipment. That isn't what I personally call a long duration.

 

[H433x0n]

Problem is not the 14900K as such, it s that in the 2 ST benchs already known they are below not only this CPU but also below the 9950X, we are no more talking of GB here but of actual browsing perf, so far the IPC in those tests is below Zen 5, i posted them in my previous post and here they are again.

Guess that currently Intel is devising about the exact power they ll use since at 250W they will have a win only in CB R20/R23 for MT, and a marginal one.

They may well set 297W as PL2, or use an extended 297W PL4 since that s their apps performance profile for ARL, otherwise they ll lose in too much benches to be convincing, so we ll surely be good for another round of exagerated TDPs.

And likely that AMD limiting their CPU at 200W has somewhat disrupted their plans as they surely expected 230W, wich would had rendered their own 250W/297W TDP acceptable.

Those aren’t verified real web browsing results. The GB5/GB6 scores are at least tangibly verified.

As far as web browsing performance, ARL seems ahead of Zen 5 in the HTML5 & text processing subtests in GB. Who knows how it ends up when we get actual benchmark results for WebXprt and Speedometer. In the IgorsLab leak, both of those were projected to be up by a decent margin.

 

[SiliconFly]

.

 

[dullard]

He has no clue what he’s talking about.

That was obvious when he confused PL2 and PL4 and then in defense again confused peak power with PL2. I'm just enjoying seeing how deep of a hole he'll dig for himself. The chart of Ryzen frequency over time was the cherry on top--it really proves that Intel is going to 297 W PL2. Somehow.

 

[SiliconFly]

.

 

[ondma]

That was obvious when he confused PL2 and PL4 and then in defense again confused peak power with PL2. I'm just enjoying seeing how deep of a hole he'll dig for himself.

He has no clue what he’s talking about. Just wants to say competition is better than intel with aome useless numbers.

Let me put it straight. ARL & competition, when it comes to power efficiency, is gonna be in the same ballpark. Overall power usage per hour under normal circumstances is gonna be very similar.

That particular poster has a long history on this forum, going back to the Bulldozer days, of being somewhat shall we say "selective" in his posts and benchmark choices. I thought he had disappeared for a while, but unfortunately he has returned. Trying to have an objective discussion with him is an exercise in futility. Better to just put him on ignore and not waste your time.

 

[SiliconFly]

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[MarkPost]

3) Lets look at that Computerbase 9950X review that you bring up. In the Blender test that you point out, the 14900K averaged 155.85 W with a peak of 274.79 W. So, to you that means intel is putting PL2 to 297 W? Really? https://www.computerbase.de/2024-08/amd-ryzen-9-9900x-9950x-test/5/

I really dont know what "average" means there, because rendering a scene with Blender doesnt sit in those suposed average values, at all.

 

[dullard]

I really dont know what "average" means there, because rendering a scene with Blender doesnt sit in those suposed average values, at all.

I assume it is what Abwx alluded to on this graph here:
https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41282823

Basically the test lets the CPU sit idle, then runs the benchmark, then lets it go idle again. That way they measure the idle power, peak power, and probably average the whole thing together. It would simulate how a user typically runs a computer (some idle, some high power) but it is not how we typically think of power consumption during a task and ignoring idle power.

From the computerbase benchmark site (translated)
"The Blender benchmark is suitable for various considerations regarding the CPU's power consumption thanks to its staggered testing method and three subtests. First, the PC does nothing for a few seconds, then it goes into full load, sometimes it is only partially loaded, and then it disappears into sleep mode again at the end. In this way, in addition to the lowest energy consumption, the maximum and an average can be derived in the test."

 

[SiliconFly]

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[igor_kavinski]

And ARL beating competition by 3.5% in performance doesn’t go well with a few. Hence unwanted diversions.

Umm...A win using 24 real threads vs. 16 real and 16 virtual threads is worth celebrating? What happens if AMD brings a 24 real core part to the party, with SMT?

 

[Wolverine2349]

Maybe a 12 p core arrow lake is coming?

Intel has Core Ultra 285K and then 265K

The 285K is 8 + 16 and 265k is 8 + 12.

Where is the 275K. It's missing. Maybe intel sandbagging and the 275k is a 12 p core only gaming chip.

Probably not but one can hope.

Though it is interesting they are skipping 275k all the way down to 265k for 8 + 16 to 8 + 12.

Makes you wonder given the i9 to i7 was 8 + 16 to 8 + 12???

 

[igor_kavinski]

Where is the 275K. It's missing.

Wrong question. Where/when 295K ??? 299K?

 

[dullard]

Wrong question. Where/when 295K ??? 299K?

Probably the 255K, 275K, and 295K numbers are reserved for Arrow Lake Refresh.

 

[igor_kavinski]

Probably the 255K, 275K, and 295K numbers are reserved for Arrow Lake Refresh.

Wouldn't they change the digit 2 to 3?

 

[jdubs03]

Wouldn't they change the digit 2 to 3?

It’s either that, or a mid cycle revision (pre-refresh) and the first digits start with 2 (akin to the X3D release). Seems a bit ambiguous how they would do it here. My guess is ARL-R will start with a 3, based on how they dealt with RPL-R.

 

[dullard]

Wouldn't they change the digit 2 to 3?

They could do that. They are just identifiers after all. But it would bump into Panther Lake numbers, making them confusing. And they'd run out of 3 digit numbers quite quickly.

They are moving from generations to series in their numbering. It makes sense to keep all Arrow Lake chips, including refreshes, in the same series.

Arrow Lake and Lunar Lake are the 2 series.

 

[DavidC1]

N3B means business afaik.

This isn't black and white you know? Intel processes and designs are absolutely optimized for high frequency. Thus it's easier for them to reach high frequencies than others. The sacrifice is density and the ability to perform well on lower clocks.

If you look at say Alderlake mobile and desktop, the desktop chip uses less voltage to reach the same frequency as the mobile part. The mobile part can't clock as high without consuming more. So why do it this way? Because battery life is determined significantly by idle power, and it is affected by leakage. The mobile parts reduce leakage significantly.

Intel themselves admit that compared to the predecessor, it has 18% perf/w gain at the lower clocks but gets to only little over 10% at the peak. It's because TSMC process has a steeper curve that benefits low power chips. They optimized it for low power on the 22nm process but after the backlash on Ivy Bridge, they must have changed it for 14nm and future process generations again.

TSMC isn't getting low power efficiency for free, and Intel isn't getting high frequency advantage for free either. They are tradeoffs each decided to make.

 

[Abwx]

So now you ignore point #1 and #2. Okay Abwx, you do you. Changing the goalpost and posting conflicting information isn't making your case though.

Up to 10 ms is the limit of time for power spikes above PL2 unless Computerbase had malfunctioning equipment. That isn't what I personally call a long duration.

For the other opoints about fixing the power so far there s no official info about the power that is dedicated for ARL, so how can you say that it s already fixed..?

As for allegedly changing the goalpost fdrom PL1 to PL2 same answer, there s no official TDP, so i can make any speculation and it cant be negated by any official number, what is sure is that at 250W they ll be good against a 253W limited 14900K but not against the competiton.

Those aren’t verified real web browsing results. The GB5/GB6 scores are at least tangibly verified.

As far as web browsing performance, ARL seems ahead of Zen 5 in the HTML5 & text processing subtests in GB. Who knows how it ends up when we get actual benchmark results for WebXprt and Speedometer. In the IgorsLab leak, both of those were projected to be up by a decent margin.

The slide at IGL say 7-10% and 9-13% for WebXPRT an Sepeedometer in respect of the 13900K wich is clocked 0.97x the 14900K, so those numbers in respect of the latter are 4-7% and 6-10% respectively, this also apply to GB btw.

 

[dullard]

For the other opoints about fixing the power so far there s no official info about the power that is dedicated for ARL, so how can you say that it s already fixed..?

As for allegedly changing the goalpost fdrom PL1 to PL2 same answer, there s no official TDP, so i can make any speculation and it cant be negated by any official number, what is sure is that at 250W

I looked up, your post still says that Intel is currently changing power levels. So, no your post it isn't fixed. I would not associate the word "fixed" with my recent posts to you.

Again you are confusing power levels. You specifically stated PL2 is going to 297 W. As "proof" you posted an estimate that PL4 is 297 W in an extreme profile of two chips. Then as more "proof" you posted a 275 W peak example (and remember peak is PL4, peak is not PL2). And now all of a sudden, out of the blue, you mention PL1. Do you know what the 4 power levels are and how they are used? For a hint, I posted the link to you.

There definitely is a set known official TDP shared between Intel, corporate customers, and suppliers. The public just haven't seen it yet from Intel. It is not currently being "devised" as you claim. You can feel free to speculate what it is, but the actual value is set in stone not currently being devised.

 

[Hulk]

Umm...A win using 24 real threads vs. 16 real and 16 virtual threads is worth celebrating? What happens if AMD brings a 24 real core part to the party, with SMT?

They will price themselves out of the game. There is a reason Intel is 8+16 currently and AMD is 16, die size.

 

[poke01]

Umm...A win using 24 real threads vs. 16 real and 16 virtual threads is worth celebrating? What happens if AMD brings a 24 real core part to the party, with SMT?

Doesn't matter One has SMT and one doesn't. What matters is the end result.

If you want really be fussy then it's 8P+16E vs 16P cores so I would say it evens out. Now if it was 24P cores on the Ultra 9 then that's not a fair comparison.

 

[majord]

They will price themselves out of the game. There is a reason Intel is 8+16 currently and AMD is 16, die size.

Doubt it.. A 24c part would wipe the floor with top arrow lake so bad it could command a decent price premium as a halo part. Not sure what chiplet sizes we'd be roughly looking at on 3nm, nothing drastic though I don't think.

 

[Hulk]

Doubt it.. A 24c part would wipe the floor with top arrow lake so bad it could command a decent price premium as a halo part. Not sure what chiplet sizes we'd be roughly looking at on 3nm, nothing drastic though I don't think.

You'll notice I wrote "currently."

That would be another chiplet. Not insignificant.

 

[Abwx]

I looked up, your post still says that Intel is currently changing power levels. So, no your post it isn't fixed. I would not associate the word "fixed" with my recent posts to you.

Again you are confusing power levels. You specifically stated PL2 is going to 297 W. As "proof" you posted an estimate that PL4 is 297 W in an extreme profile of two chips. Then as more "proof" you posted a 275 W peak example (and remember peak is PL4, peak is not PL2). And now all of a sudden, out of the blue, you mention PL1. Do you know what the 4 power levels are and how they are used? For a hint, I posted the link to you.

There definitely is a set known official TDP shared between Intel, corporate customers, and suppliers. The public just haven't seen it yet from Intel. It is not currently being "devised" as you claim. You can feel free to speculate what it is, but the actual value is set in stone not currently being devised.

If you know something about Intel s communications with OEMs please let us know, for the time the general public is aware of nothing and can rely only on past Intel s behaviours.