Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Exist50]

What is Intel making on N3 for mobile?

Arrow Lake and/or Lunar Lake, probably.

 

[Exist50]

View attachment 66493

If you're going to post an unofficial composite image, you should make it clear that the pic isn't real. There has not been a single leak or word on an 8+16 die.

 

[nicalandia]

If you're going to post an unofficial composite image, you should make it clear that the pic isn't real. There has not been a single leak or word on an 8+16 die.

It's one the many mockups from Locuza

 

[igor_kavinski]

Arrow Lake and/or Lunar Lake, probably.

So they are gonna start stockpiling chips a year early for that?

 

[Exist50]

It's one the many mockups from Locuza

Exactly. It's a mockup, nothing more.

 

[dullard]

So they are gonna start stockpiling chips a year early for that?

You start initial test production a year early. When they do pass testing after several iterations, since TSMC is quite limited in initial N3 capacity, then you do start stockpiling.

 

[Exist50]

@Exist50 The number of Xe cores being 4-16 shown above equals 64-192 EUs. If we believe some leaks are intentional we can also speculate it's meant to obfuscate.

I wouldn't read that much into it.

Honestly, this whole presentation was quite a letdown. Pretty much all stuff we already knew, and very little about Meteor Lake in particular.

 

[uzzi38]

Apple and Intel become first to adopt TSMC's latest chip tech

Taiwanese company remains vital partner for American tech giants

asia.nikkei.com

You've been warned before yet i'll inform you once again. You must include your own personal commentary when dropping links or other members quotes.

Daveybrat
AT Moderator

How is this a "confirmation"?

This is nothing more than a rumour.

 

[Markfw]

How is this a "confirmation"?

This is nothing more than a rumour.

But he works for Intel, where rumor becomes fact !!

 

[stebler]

The MTL GPU having versions with 64, 128 and 192 EUs matches the driver entries from last December https://forums.anandtech.com/thread...ally-launch-in-the-west.2526376/post-40656013.

 

[DrMrLordX]

It's one the many mockups from Locuza

. . . oh.

 

[dullard]

@Exist50 The number of Xe cores being 4-16 shown above equals 64-192 EUs.

Am I missing something, or does the number of graphics Xe cores scale from 4 to 12 (not 16)? I suppose 16 could happen, but I'm not seeing it in the images.

 

[mikk]

Maybe 192EU is a special variant like the GT3/GT4 on Haswell or Broadwell? Regular and initial MTL gets 128EUs, the old GT2. 64EU tile comparable to the old GT1.

 

[Exist50]

Maybe 192EU is a special variant like the GT3/GT4 on Haswell or Broadwell? Regular and initial MTL gets 128EUs, the old GT2. 64EU tile comparable to the old GT1.

Once upon a time, perhaps, but no longer.

 

[IntelUser2000]

Am I missing something, or does the number of graphics Xe cores scale from 4 to 12 (not 16)? I suppose 16 could happen, but I'm not seeing it in the images.

View attachment 66534

You are right, my bad. It's 12 and 192.

 

[IntelUser2000]

So, similar to the Quark core on the Lewisburg PCH?

Not at all. This core will be an order of magnitude faster. This might be best described as a core fast enough to handle Windows idle duty on the chipset. The x86 platforms need to reel in the active threads down as fast as possible and this is likely the chip dedicated to do it.

Quark is barely fast enough to handle the relatively primitive compute a PCH needs.

 

[burninatortech4]

Not at all. This core will be an order of magnitude faster. This might be best described as a core fast enough to handle Windows idle duty on the chipset. The x86 platforms need to reel in the active threads down as fast as possible and this is likely the chip dedicated to do it.

Quark is barely fast enough to handle the relatively primitive compute a PCH needs.

I wasn't aware there was any "processing" being done on the PCH. At least in a way that was somewhat transparent to an OS.

 

[SpudLobby]

What are they going to run on those ULV cores? They will obviously be above a quark, probably some Tremont-esque derivative.

It's not clear what all they're really going to be able to accomplish beyond shutting off the compute tile for things like video per se - and to be fair this probably will be a notable win, presumably the idle cores can then manage very basic background tasks, networking.

But do you really want those ULV cores handling interactive threads? What's the power on/switching latency like for the compute tile then - ideally they have competent profiling going on for this via some microcontroller to handle transitions, and they certainly will, but some of these choices will be up to Intel on the margin for better and worse.

I'd rather just see them do the E-Cores & ring idle power correctly to begin with, or at least rivaling AMD's Rembrandt on idle power without this contraption, but oh well.

 

[Exist50]

They will obviously be above a quark, probably some Tremont-esque derivative.

I'm about 90% sure they're (full) Crestmont. The remaining 10% being the possibility that they're still Gracemont, but absolutely not anything less.

Ideally, they'll be strong enough to handle things like streaming video and scrolling through a web page without waking the compute die much, but we'll see. I think software will be the big question. 3 tiers of power/performance will be a test of the Windows scheduler.

 

[Joe NYC]

I'm about 90% sure they're (full) Crestmont. The remaining 10% being the possibility that they're still Gracemont, but absolutely not anything less.

Ideally, they'll be strong enough to handle things like streaming video and scrolling through a web page without waking the compute die much, but we'll see. I think software will be the big question. 3 tiers of power/performance will be a test of the Windows scheduler.

I have to respond to this with Scott Adams quote many Civilization players are familiar with:

Normal people... believe that if it ain't broke, don't fix it. Engineers believe that if it ain't broke, it doesn't have enough features yet.

It seems to me that Meteor Lake has been designed using this philosophy.

 

[jpiniero]

I have to respond to this with Scott Adams quote many Civilization players are familiar with:

Normal people... believe that if it ain't broke, don't fix it. Engineers believe that if it ain't broke, it doesn't have enough features yet.

It seems to me that Meteor Lake has been designed using this philosophy.

It is broke...

 

[Joe NYC]

It is broke...

haha, I kind of think so too, but wanted to give it a benefit of doubt.

 

[SpudLobby]

I'm about 90% sure they're (full) Crestmont. The remaining 10% being the possibility that they're still Gracemont, but absolutely not anything less.

Ideally, they'll be strong enough to handle things like streaming video and scrolling through a web page without waking the compute die much, but we'll see. I think software will be the big question. 3 tiers of power/performance will be a test of the Windows scheduler.

Crestmont is possible. I will be more optimistic if it is the case. Idling for streaming video won’t be so much of a big deal, but interactive tasks they’d want to be careful short of compromising UX, and Crestmont would be fine for that. Indeed, the migration policy and heuristics for QoS is where Microsoft also comes into play. I wonder what the timescales are for powering the compute tile on/off with Foveros and migrating a thread. Suppose it depends how this is implemented.

Really they ought to have focused on fixing their ring’s idle power issues as opposed to adding this layer of complexity. How are AMD getting away with 8 big (smaller than Intel’s big by a smidgen but still) cores and reaping low static power draw too with Rembrandt? Firmware changes for one thing, but what engineering compromise makes Alder Lake’s idle and sub-10-15W power consumption so awful, even relative to their own previous 10/7NM products?

Pushing frequencies and Gracemont’s prioritizing of area efficiency over energy efficiency doesn’t help, but that’s not what I’m getting toward here and we know that. Something is rotten with their uncore/fabric.

 

[moinmoin]

How are AMD getting away with 8 big (smaller than Intel’s big by a smidgen but still) cores and reaping low static power draw too with Rembrandt?

Granularity of the subdivision of the SoC design as well as continued development on those.

With the introduction of Infinity Fabric (especially scalable control fabric) AMD introduced the ability to monitor and control ever more distinct areas within the chips. They make use of this for further development by extending the granularity of power gating as well as optimizing for power efficiency all interconnections within the chips.

Meanwhile Intel appears to be still using the same static over a decade old ring bus design as well as the same mesh fabric (which actually decreased power efficiency further, so is not a replacement in that regard) since over half a decade. I think/hope we are just seeing outdated designs so far and Intel actually has some progressive design coming, but the wait is quite long already.

 

[Joe NYC]

Granularity of the subdivision of the SoC design as well as continued development on those.

With the introduction of Infinity Fabric (especially scalable control fabric) AMD introduced the ability to monitor and control ever more distinct areas within the chips. They make use of this for further development by extending the granularity of power gating as well as optimizing for power efficiency all interconnections within the chips.

Meanwhile Intel appears to be still using the same static over a decade old ring bus design as well as the same mesh fabric (which actually decreased power efficiency further, so is not a replacement in that regard) since over half a decade. I think/hope we are just seeing outdated designs so far and Intel actually has some progressive design coming, but the wait is quite long already.

BTW, I seriously doubt viability of Meteor Lake in the marketplace. A mini Ponte Vecchio is market that values low cost, low power and small size (cost competitive Ultra Portable segment).

Meteor Lake may hold its own in larger, higher performance desktop replacement segment.

AMD already has a good product in this market, Rembrandt. With annual cadence, there will be N4 Phoenix already established in the market before Meteor Lake launches, and another iteration (Strix?) shortly after.

AMD is opportunistic and practical in what advanced packaging is deployed where. As opposed to Intel, which, it seems, issued orders to force march its army to chiplets.

Ponte Vecchio is already the first victim and Meteor Lake may be another...