Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[SarahKerrigan]

You are missing a point. Intel P-cores aim to be 1T performance king.

Intel aims for a lot of things. How many of them have they hit i the last five years?

Competition is though nowadays - 1T performance crown won't come easily. SMT isn't a free lunch anymore, core to target 1T need to drop it and only AMD seems to disagree now.

Z is overwhelmingly single-thread prioritized... and it has SMT.

Still haven't seen any actual methodology for what you're claiming beyond "Intel sez."

 

[StinkyPinky]

So I guess laptops with 64GB of ram is now a distant memory for Intel?

 

[TwistedAndy]

I'm not too concerned about SMT. In ideal conditions, it can provide nearly 15-20% higher CB R23 score.

On the other hand, SMT increases power consumption, increases the die area, and can decrease the performance in some cases. Actually, Intel engineers admitted that they even disable SMT dynamically in some applications.

From my perspective, it's more efficient to scale the MT performance by increasing the number of E-cores. But from the other side, I can hardly imagine how I can load 24 cores.

 

[Nothingness]

Intel aims for a lot of things. How many of them have they hit i the last five years?

You're being nice. Remember the 14nm delays? That was 10 years ago.

 

[SiliconFly]

-

 

[naukkis]

Z is overwhelmingly single-thread prioritized... and it has SMT.

Actually would like to see Z spec results. IBM did shout about single-thread performance leadership few years ago but not anymore - pretty sure that they too faced some pretty serious competition from non-smt rival designs.

 

[SarahKerrigan]

Actually would like to see Z spec results. IBM did shout about single-thread performance leadership few years ago but not anymore - pretty sure that they too faced some pretty serious competition from non-smt rival designs.

Z single-thread perf is superb. I can't provide you SPEC results, though I've run them, but it's the real deal.

 

[naukkis]

Z single-thread perf is superb. I can't provide you SPEC results, though I've run them, but it's the real deal.

See that there isn't any extreme performance-oriented SMT-less design out yet. Intel seems to be first - if have to bet I would say that's Keller effect there and in AMD too, staying with SMT. Apple might target higher performance levels too.

 

[KompuKare]

What we currently only have is Intel marketeers going on about how removing SMT is so great.

Not any technical papers being presented at a technical show, or similar.

Until proven otherwise, I am inclined to think that the explainion is indeed what @Abwx speculated:

For Intel's hybrid approach to really work well, they needs the two type of cores to be as close to each other as possible. Dropping AVX-512 - after all the years of hype - and how SMT make the most sense in this context.

They also seem to have really pushed their synthesised design tools prowess so it is possible that some server chips addressing a certain market may get AVX-512 or some other "niche" feature anyhow.

Although the longer mainstream doesn't have the feature, the less chance of that IMO as While everyone is margins crazy, high volume with more modest margins is hugely important - and mainly why TSMC doing billions of ARM chips managed to be so successful. Intel of yore with the cast-off Atom stepchild attitude did not want to do higher volume, lower margins. Ironic of we consider how the cludge which is x86 ended up beating everyone else in the 80s and 90s - volume, volume, volume.

 

[LightningZ71]

Actually would like to see Z spec results. IBM did shout about single-thread performance leadership few years ago but not anymore - pretty sure that they too faced some pretty serious competition from non-smt rival designs.

Spec dot org has results for the E1050 96 core. Just do a search on google for spec results for ibm power processors and it's one of the first entries.

To give you some perspective:
IBM Power E1050 (2.95 - 3.90 GHz, 96 core, AIX) - [768 instances, 4 chips, SMT8, only 2 threads per core in use) SpecRate2017IntBase=1220 , Peak=1580
IBM Power E1080 (3.55 - 4 GHz, 120 core, AIX) - [120 cores, 8 chips, 960 instances] = SpecRate2017IntBase=1700 , Peak=2170
Kaytus KR1280E2 (AMD EPYC 9754) (256 cores/512 instances) - SpecRate2017IntBase=1930 , Peak=2100
Kaytus KR1280E2 (AMD EPYC 9654) (192 cores/384 instances) - SpecRate2017IntBase=1800 , Peak=1920
Dell PowerEdge R6625 (AMD EPYC 9754 128-Core Processor)- (256 cores/512 instances) = SpecRate2017IntBase=1820 , Peak=1980
Dell PowerEdge R6625 (AMD EPYC 9684X 96-Core Processor) - (192 cores/384 instances) = SpecRate2017IntBase=1790 , Peak=1870
ZTE R8500G5 Server System (1.90 GHz, Intel Xeon Platinum 8490H) - (240 cores/480 instances) = SpecRate2017IntBase=2000 , Peak=2050
HPE Compute Scale-up Server 3200 (1.90 GHz, Intel Xeon Platinum 8490H) - (960 cores/1920 instances) - SpecRate2017IntBase=7310 , Peak=[Not submitted]

IBM Power10 can be configured in a performance competitive manner, but, it doesn't look like they are competitive on a "per-core-throughput" basis.

 

[SiliconFly]

-

 

[KompuKare]

Hilarious! When you say "volume, volume, volume", AMD is not even in the radar compared to Intel.

And I keep saying the same thing about AMD, especially their GPUs.
What's the point of developing a new design with huge fixed costs, overpricing it at launch getting poor reviews, poor sales, and in the end reducing the price when that generation is almost gone?

But my point about Intel and why they failed so long with Atom, did not want the iPhone SOC business, etc., still stands: avoiding volume in a quest for margins is a very dangerous thing. And that the disciplineyou onlyget by making mass market products is very important but easy for bean counters to miss.

 

[SiliconFly]

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[Hulk]

While I'm interested in the increased performance of ARL and Zen 5 and the tech behind it, honestly my 14900K desktop is quite "healthy" for my heavy workloads.

What I'm really interested in is a LNL laptop to replace my seriously outdated MS Surface Laptop 2 rocking 4 low frequency Skylake cores (8250u).

 

[SiliconFly]

-

 

[Magio]

Is a fair assumption from those SKUs leaks that the plans to have LNL support fanless designs have been shelved for now? They also haven't mentioned anything about that at Computex.

I don't personally care much about fanless, I'd rather have a fan and a more powerful chip, but Intel being confident about LNL at 8W would have been very encouraging for what to expect from it at 17W.

 

[SiliconFly]

-

 

[Wolverine2349]

Just saw MLID's video talking to HY.

To summarize HY's thoughts on ARL's LNC: Lunar Lake's LNC has 14% IPC uplift. Loss due to clock regression around 5%. ARL's LNC is expected to have more IPC uplift than Lunar Lake's LNC. Not sure exactly how much, but expecting around 20%. Even after adjusting for clock regression, it still comes around 15%.

I think it may even be more! Like 20% final is even possible. ARL might take both the ST crown and MT as well this generation.

That would be great. Some have said in this thread I was setting up for disappointment for hoping for anything more than 14% IPC uplift. 20% would be really nice.

And want platinum stability back as well. 13th and 14th Gen were a mess in terms of stability degradation even though they were extremely performant.

If 20% IPC uplift is true Intel will take crown easily handily over Ryzen 9000 with Arrow Lake. Maybe even take gaming crown and certainly in the thread heavy games over Ryzen 9000X3D. Certainly at least trade blows with 9800X33D or maybe even a little ahead for games that max 5-8 cores and beat 9950X3D due to cross CCX/CCD latency hit which Intel does not have the problem with.

Maybe Conroe lite moment for Intel with Arrow Lake would be so cool.

 

[ondma]

What we currently only have is Intel marketeers going on about how removing SMT is so great.

Not any technical papers being presented at a technical show, or similar.

Until proven otherwise, I am inclined to think that the explainion is indeed what @Abwx speculated:

For Intel's hybrid approach to really work well, they needs the two type of cores to be as close to each other as possible. Dropping AVX-512 - after all the years of hype - and how SMT make the most sense in this context.

They also seem to have really pushed their synthesised design tools prowess so it is possible that some server chips addressing a certain market may get AVX-512 or some other "niche" feature anyhow.

Although the longer mainstream doesn't have the feature, the less chance of that IMO as While everyone is margins crazy, high volume with more modest margins is hugely important - and mainly why TSMC doing billions of ARM chips managed to be so successful. Intel of yore with the cast-off Atom stepchild attitude did not want to do higher volume, lower margins. Ironic of we consider how the cludge which is x86 ended up beating everyone else in the 80s and 90s - volume, volume, volume.

Yea, we never heard anybody speculating how great it would be to remove HT until it came out that newer Intel designs would not have it. Now it is being proclaimed as the greatest thing since sliced bread. A classical case of rationalization, IMO. As I said before, removing HT might have been worthwhile if it had allowed a huge increase in ST performance. Granted we dont have final data yet, but it seems that the final ST gain for ARL will be very similar to previous generational gains from Intel that did not sacrifice hyperthreading.

 

[H433x0n]

Yea, we never heard anybody speculating how great it would be to remove HT until it came out that newer Intel designs would not have it. Now it is being proclaimed as the greatest thing since sliced bread. A classical case of rationalization, IMO. As I said before, removing HT might have been worthwhile if it had allowed a huge increase in ST performance. Granted we dont have final data yet, but it seems that the final ST gain for ARL will be very similar to previous generational gains from Intel that did not sacrifice hyperthreading.

The effects of HT have been dwindling and the costs have been rising every generation. There has now been 10+ years of security vulnerabilities and the effects of that have cascaded to the point where the pros/cons are not as clean cut as it was 10 years ago. There are more duplicated structures to compensate for these vulnerabilities and that has also led to an increase cost of validation. If all else is equal, would I prefer HT be on Lion Cove? Yes. Do I think that it's a must have feature? No.

I view HT as basically a ~neutral feature. It's helpful for nT performance sure but ARL-S will come equipped 24 physical cores including 16 Skymont cores that will boost nT performance by a decent chunk.

 

[Doug S]

Yea, we never heard anybody speculating how great it would be to remove HT until it came out that newer Intel designs would not have it. Now it is being proclaimed as the greatest thing since sliced bread. A classical case of rationalization, IMO. As I said before, removing HT might have been worthwhile if it had allowed a huge increase in ST performance. Granted we dont have final data yet, but it seems that the final ST gain for ARL will be very similar to previous generational gains from Intel that did not sacrifice hyperthreading.

I think a lot of people would have been arguing a LOT more strongly against HT if we knew how big the die penalty had become. It was claimed to be 5% originally which was pretty minor - and when HT hit the scene it wasn't like additional cores were an option since dual core was only just appearing on the scene since you can't have 1.05 or 2.10 cores. Few people reading this are actually architects, we didn't know about the increasing penalty for implementation of HT until it was pointed out by someone in the position to know.

Even if there was zero gain in ST as a consequence of HT's removal if you save 15% of die area in your cores that means you can have 15% more cores to provide MT uplift. And not the kind of "single digit gains here, 20% there, oops bit of a regression here, oh hey here's one outlier we can point to that gains 30%" uplift that HT gives, but 15% across the board. And no static power penalty, given that you can't effectively gate those extra transistors sprinkled across the core so you're paying a penalty in static/idle power over cores that don't implement HT.

And that's before you get into the additional man hours required for design and validation, and the security headaches we've seen with side channels for processes sharing a physical core.

 

[Henry swagger]

Apple showed smt is not that special.. intel are looking at apple because apple are the gold standard on high performance on laptops

 

[Henry swagger]

Just saw MLID's video talking to HY.

To summarize HY's thoughts on ARL's LNC: Lunar Lake's LNC has 14% IPC uplift. Loss due to clock regression around 5%. ARL's LNC is expected to have more IPC uplift than Lunar Lake's LNC. Not sure exactly how much, but expecting around 20%. Even after adjusting for clock regression, it still comes around 15%.

I think it may even be more! Like 20% final is even possible. ARL might take both the ST crown and MT as well this generation.

As i said 25% is possible over raptor 😁.. thry want to double golden cove ipc by cougar cove time 😀

 

[QuickyDuck]

15% improvement from optimization sounds too good to be true for me.
It can be done only if prior intel core were poorly designed which I don't think it is?

 

[Hulk]

LNL Lion Cove is +14%. History would suggest ARL Lion Cove will differ only by the addition of a faster memory subsystem and cache structure and as such I would expect at most an additional 5% IPC and mainly in applications that can utilize more L3, like games. So I'm prediction max IPC increase for Lion Cove at 19%.

As for the lack of HT, it made no sense to me either until Gracemont morphed into Skymont with Raptor Cove IPC at 1/3 the area. That's a game changer for MT and does seem to make ST moot for the big cores. It also has the additional benefit of simplifying things for the Thread Director.