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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






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PPT3.jpg



As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Idk how many times I say this, and you just ignore it, but again, it's literally only MLID who expects a high performance uplift. Literally everyone else, Xino, Raichu, etc etc all say the perf uplift is gonna be ~10% over RPL.
Intel "may" have a contingency plan to deal with a repeat of a Zen 3 like situation by now. They kinda kept themselves competitive with Raptor Lake by increasing the cache sizes. Who knows what they might do with Arrow Lake. Maybe ditch the original ARL design and go with the Refresh design with increased cache sizes for the ARL debut? They could also include a more powerful iGPU tile with each ARL desktop part and poke fun at AMD's puny iGPU? They could even go with a hybrid strategy where the original ARL design is used in lower end CPUs with disabled cores to avoid chucking the already manufactured dies and keeping the refresh dies for their high end parts.
 
ntel "may" have a contingency plan to deal with a repeat of a Zen 3 like situation by now.
wut
They kinda kept themselves competitive with Raptor Lake by increasing the cache sizes.
I don't think the increased cache sizes did much. In gaming the increased L2s just had an increased PPC of like ~5% in gaming. It was mostly just clocks + more cores.
Maybe ditch the original ARL design and go with the Refresh design with increased cache sizes for the ARL debut?
If ARL-R had increased cache sizes they wouldn't be calling it ARL-R, it would be called something else IMO.
 
Idk how many times I say this, and you just ignore it, but again, it's literally only MLID who expects a high performance uplift. Literally everyone else, Xino, Raichu, etc etc all say the perf uplift is gonna be ~10% over RPL.
MLID says 25-35% higher performance than Raptor Lake, which is presumably MT perf. Raichu says 15% IPC improvement, and 10% ST perf uplift over RPL refresh i.e. 14900K.

I don't see how these two claims are incompatible with each other.
 
MLID says 25-35% higher performance than Raptor Lake, which is presumably MT perf. Raichu says 15% IPC improvement, and 10% ST perf uplift over RPL refresh i.e. 14900K.

I don't see how these two claims are incompatible with each other.
Well, first of all, we are talking about LNC performance, not MT perf in general.
Second of all, MLID thinks the ST perf is gonna be "at least 25%" higher than RPL.
And both were helped by the increased cache availability. Their performance uplift would've been smaller with the original Alder Lake caches
The L2 cache increase only netted like an ~5% gain in PPC in gaming.
 
How can ARL be 25% higher than MTL in MT workloads without hyperthreading? That points to a pretty serious ST uplift or extremely strong performance by them Skymonts. I think the latter seems more likely.
 
The older info doesn't contradict the newer info.
I didn't say that it contradicts the older info. The two leaks aren't comparable because they talk about different things. The older leak speaks of ST perf gain over Raptor Lake, and the newer leak is about (presumably) overall performance over MTL at same core count. If we go by this statement, then it is reasonable to assume that MLID is talking about ARL-H and not ARL-S in the second leak.

However, like I said before, newer leaks from a credible leaker usually takes precedence over older leaks from the same leaker. However, since MLID is all over the place when it comes to accuracy of his leaks, it is hard to make a judgment call.
 
I didn't say that it contradicts the older info. The two leaks aren't comparable because they talk about different things. The older leak speaks of ST perf gain over Raptor Lake, and the newer leak is about (presumably) overall performance over MTL at same core count. If we go by this statement, then it is reasonable to assume that MLID is talking about ARL-H and not ARL-S in the second leak.

However, like I said before, newer leaks from a credible leaker usually takes precedence over older leaks from the same leaker. However, since MLID is all over the place when it comes to accuracy of his leaks, it is hard to make a judgment call.
Ok.
 
wut

I don't think the increased cache sizes did much. In gaming the increased L2s just had an increased PPC of like ~5% in gaming. It was mostly just clocks + more cores.

If ARL-R had increased cache sizes they wouldn't be calling it ARL-R, it would be called something else IMO.
Raptor Lake technically had "more cores", but they were E cores. I dont think that had much if anything to do with gaming. Hopefully, though, Intel (and the game developers) will eventually find a way to utilize the E cores. Otherwise, Intel will be in serious trouble if cpu demands in future games with ever more powerful GPUs exceed what 8 big cores can deliver.
 
Intel "may" have a contingency plan to deal with a repeat of a Zen 3 like situation by now. They kinda kept themselves competitive with Raptor Lake by increasing the cache sizes. Who knows what they might do with Arrow Lake. Maybe ditch the original ARL design and go with the Refresh design with increased cache sizes for the ARL debut? They could also include a more powerful iGPU tile with each ARL desktop part and poke fun at AMD's puny iGPU? They could even go with a hybrid strategy where the original ARL design is used in lower end CPUs with disabled cores to avoid chucking the already manufactured dies and keeping the refresh dies for their high end parts.
Arrow Lake is already set in stone. Intel most likely already has silicon back from the fab.
 
True. Tape-in to manufacturing easily takes more than year. Can't do major changes this late in the cycle. Everything would be locked in.
What if they have TWO ARL designs? One easier/cheaper and the other harder/expensive and they decide to go with the harder one if they absolutely need to.
 
What if they have TWO ARL designs? One easier/cheaper and the other harder/expensive and they decide to go with the harder one if they absolutely need to.
Intel already has 3 designs for 2024: MTL, ARL, LNL.
Within those 3, they have variants with different P+E cores.

I highly doubt they would have a 4th, separate design. There is always next year (or so), and Panther Lake (or whatever comes after ARL).
 
That makes no sense in context of what Raichu said. He said and I quote "it's easy to get 3 meters".
Could that mean that 3 nm was not as difficult as expected? Could it mean that 3 nm has higher yield than originally expected? Could it mean that the 3 nm foundry is available to use? Could it mean that the 3 nm foundry is underutilized so you don't have to fight other companies for limited space? I could see many ways that the context of that phrase could apply to 3 nm.
 
MLID likes to play both sides with intel leaks, he'll say the best possible thing about prospective performance while also being one of the first to report when the new process has eaten you-know-what on the pavement in front of a school bus of gawking children. I always take those perf figures with a mountain of salt, but he's been pretty rock solid on the actual comings and goings of intel architectures for a minute now.

With that said, you can't give too much creedence to the sky-high projections for IPC/ST. He's definitely better on the negative side of the rumor mill.
 
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